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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:08 -0500
commit09cc401848a7ee4540639ab8a05b40a4e1a7ee0a (patch)
tree812102f32eebc34d42058796ff2bb80688a4c978 /src/arch/arm
parentb1158e493843066acdba153c89573273f5d0fd73 (diff)
downloadgem5-09cc401848a7ee4540639ab8a05b40a4e1a7ee0a.tar.xz
ARM: Implement the ubfx and sbfx instructions.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/insts/misc.isa21
1 files changed, 21 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index d7fa310b7..e3c3132d9 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -458,4 +458,25 @@ let {{
header_output += BasicDeclare.subst(nopIop)
decoder_output += BasicConstructor.subst(nopIop)
exec_output += BasicExecute.subst(nopIop)
+
+ ubfxCode = '''
+ Dest = bits(Op1, imm2, imm1);
+ '''
+ ubfxIop = InstObjParams("ubfx", "Ubfx", "RegRegImmImmOp",
+ { "code": ubfxCode,
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegImmImmOpDeclare.subst(ubfxIop)
+ decoder_output += RegRegImmImmOpConstructor.subst(ubfxIop)
+ exec_output += PredOpExecute.subst(ubfxIop)
+
+ sbfxCode = '''
+ int32_t resTemp = bits(Op1, imm2, imm1);
+ Dest = resTemp | -(resTemp & (1 << (imm2 - imm1)));
+ '''
+ sbfxIop = InstObjParams("sbfx", "Sbfx", "RegRegImmImmOp",
+ { "code": sbfxCode,
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegImmImmOpDeclare.subst(sbfxIop)
+ decoder_output += RegRegImmImmOpConstructor.subst(sbfxIop)
+ exec_output += PredOpExecute.subst(sbfxIop)
}};