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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:05 -0500 |
| commit | 1884ed65bd7791315d111835888d4a83d78e204a (patch) | |
| tree | b5d86eb4ea3351f555d26db6303638deab416f5a /src/arch/arm | |
| parent | ff3b21bc2bef25c37104b1a62d338e61ba55ff80 (diff) | |
| download | gem5-1884ed65bd7791315d111835888d4a83d78e204a.tar.xz | |
ARM: Decode MRS and MSR for thumb.
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa/formats/branch.isa | 29 |
1 files changed, 21 insertions, 8 deletions
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index e03fbfda3..865a73b32 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -110,7 +110,6 @@ def format Thumb32BranchesAndMiscCtrl() {{ { const uint32_t op = bits(machInst, 26, 20); const uint32_t op1 = bits(machInst, 14, 12); - const uint32_t op2 = bits(machInst, 11, 8); switch (op1 & 0x5) { case 0x0: if (op == 127) { @@ -134,14 +133,19 @@ def format Thumb32BranchesAndMiscCtrl() {{ } else { switch (op) { case 0x38: - if ((op2 & 0x3) == 0) { - // Application level - return new WarnUnimplemented("msr", machInst); + { + const IntRegIndex rn = + (IntRegIndex)(uint32_t)bits(machInst, 19, 16); + const uint8_t byteMask = bits(machInst, 11, 8); + return new MsrCpsrReg(machInst, rn, byteMask); } - // Fall through on purpose... case 0x39: - // System level - return new WarnUnimplemented("msr", machInst); + { + const IntRegIndex rn = + (IntRegIndex)(uint32_t)bits(machInst, 19, 16); + const uint8_t byteMask = bits(machInst, 11, 8); + return new MsrSpsrReg(machInst, rn, byteMask); + } case 0x3a: { const uint32_t op1 = bits(machInst, 10, 8); @@ -198,8 +202,17 @@ def format Thumb32BranchesAndMiscCtrl() {{ imm32, false); } case 0x3e: + { + const IntRegIndex rd = + (IntRegIndex)(uint32_t)bits(machInst, 11, 8); + return new MrsCpsr(machInst, rd); + } case 0x3f: - return new WarnUnimplemented("mrs", machInst); + { + const IntRegIndex rd = + (IntRegIndex)(uint32_t)bits(machInst, 11, 8); + return new MrsSpsr(machInst, rd); + } } break; } |