diff options
author | Gabe Black <gabeblack@google.com> | 2018-10-18 17:34:08 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:15:45 +0000 |
commit | 230b892fa3f484a46f4cd77f889f8793416b91e2 (patch) | |
tree | 53b32ed7120d019399e36d04655487745bbba9ee /src/arch/arm | |
parent | 774770a6410abb129e2a19de1ca50d7c0c311fef (diff) | |
download | gem5-230b892fa3f484a46f4cd77f889f8793416b91e2.tar.xz |
arch: cpu: Stop passing around misc registers by reference.
These values are all basic integers (specifically uint64_t now), and
so passing them by const & is actually less efficient since there's a
extra level of indirection and an extra value, and the same sized value
(a 64 bit pointer vs. a 64 bit int) is being passed around.
Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3
Reviewed-on: https://gem5-review.googlesource.com/c/13626
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/isa.cc | 4 | ||||
-rw-r--r-- | src/arch/arm/isa.hh | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index ba7c09509..6cbf8db90 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -710,7 +710,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) } void -ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val) +ISA::setMiscRegNoEffect(int misc_reg, RegVal val) { assert(misc_reg < NumMiscRegs); @@ -732,7 +732,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const RegVal &val) } void -ISA::setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc) +ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) { RegVal newVal = val; diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh index c365a1bd0..60c572833 100644 --- a/src/arch/arm/isa.hh +++ b/src/arch/arm/isa.hh @@ -430,8 +430,8 @@ namespace ArmISA public: RegVal readMiscRegNoEffect(int misc_reg) const; RegVal readMiscReg(int misc_reg, ThreadContext *tc); - void setMiscRegNoEffect(int misc_reg, const RegVal &val); - void setMiscReg(int misc_reg, const RegVal &val, ThreadContext *tc); + void setMiscRegNoEffect(int misc_reg, RegVal val); + void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc); RegId flattenRegId(const RegId& regId) const |