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authorSteve Reinhardt <steve.reinhardt@amd.com>2010-03-23 08:50:57 -0700
committerSteve Reinhardt <steve.reinhardt@amd.com>2010-03-23 08:50:57 -0700
commit4d77ea7a5783d1de87a8eb804b17a6ef352998ce (patch)
treefbf1fd950e46885fdca93abbaf689f5131752995 /src/arch/arm
parentd484e1b334c6fd3f2721a2a4628c2324ed14fd08 (diff)
downloadgem5-4d77ea7a5783d1de87a8eb804b17a6ef352998ce.tar.xz
cpu: fix exec tracing memory corruption bug
Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/formats/mem.isa2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 0b0a4c9fa..2f66ca54e 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -172,7 +172,6 @@ def template StoreExecute {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
if (fault == NoFault) {
@@ -204,7 +203,6 @@ def template StoreInitiateAcc {{
if (fault == NoFault) {
fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
memAccessFlags, NULL);
- if (traceData) { traceData->setData(Mem); }
}
// Need to write back any potential address register update