Registers: Add a registers.hh file as an ISA switched header.

This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh

8 files changed, 165 insertions, 219 deletions

diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index ea55314a4..7244252d8 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -41,7 +41,6 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/static_inst.cc')
     Source('isa.cc')
     Source('pagetable.cc')
-    Source('regfile.cc')
     Source('tlb.cc')
     Source('vtophys.cc')
 
diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index d670d673d..542174b6b 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -33,7 +33,6 @@
 #ifndef __ARCH_ARM_ISA_TRAITS_HH__
 #define __ARCH_ARM_ISA_TRAITS_HH__
 
-#include "arch/arm/max_inst_regs.hh"
 #include "arch/arm/types.hh"
 #include "base/types.hh"
 
@@ -46,8 +45,6 @@ class StaticInstPtr;
 namespace ArmISA
 {
     using namespace LittleEndianGuest;
-    using ArmISAInst::MaxInstSrcRegs;
-    using ArmISAInst::MaxInstDestRegs;
 
     StaticInstPtr decodeInst(ExtMachInst);
 
@@ -98,36 +95,6 @@ namespace ArmISA
     // return a no-op instruction... used for instruction fetch faults
     const ExtMachInst NoopMachInst = 0x00000000;
 
-    // Constants Related to the number of registers
-    const int NumIntArchRegs = 16;
-    const int NumIntSpecialRegs = 19;
-    const int NumFloatArchRegs = 16;
-    const int NumFloatSpecialRegs = 5;
-    const int NumInternalProcRegs = 0;
-
-    const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
-    const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
-
-    // semantically meaningful register indices
-    const int ReturnValueReg = 0;
-    const int ReturnValueReg1 = 1;
-    const int ReturnValueReg2 = 2;
-    const int ArgumentReg0 = 0;
-    const int ArgumentReg1 = 1;
-    const int ArgumentReg2 = 2;
-    const int ArgumentReg3 = 3;
-    const int FramePointerReg = 11;
-    const int StackPointerReg = 13;
-    const int ReturnAddressReg = 14;
-    const int PCReg = 15;
-
-    const int ZeroReg = NumIntArchRegs;
-    const int AddrReg = ZeroReg + 1; // Used to generate address for uops
-
-    const int SyscallNumReg = ReturnValueReg;
-    const int SyscallPseudoReturnReg = ReturnValueReg;
-    const int SyscallSuccessReg = ReturnValueReg;
-
     const int LogVMPageSize = 12;	// 4K bytes
     const int VMPageSize = (1 << LogVMPageSize);
 
@@ -137,10 +104,6 @@ namespace ArmISA
     const int WordBytes = 4;
     const int HalfwordBytes = 2;
     const int ByteBytes = 1;
-
-    // These help enumerate all the registers for dependence tracking.
-    const int FP_Base_DepTag = NumIntRegs;
-    const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
 };
 
 using namespace ArmISA;
diff --git a/src/arch/arm/misc_regfile.hh b/src/arch/arm/misc_regfile.hh
index e89826956..6cafc524f 100644
--- a/src/arch/arm/misc_regfile.hh
+++ b/src/arch/arm/misc_regfile.hh
@@ -31,8 +31,7 @@
 #ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 #define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
 
-#include "arch/arm/isa_traits.hh"
-#include "arch/arm/miscregs.hh"
+#include "arch/arm/registers.hh"
 #include "arch/arm/types.hh"
 #include "sim/faults.hh"
 
@@ -40,9 +39,8 @@ class ThreadContext;
 
 namespace ArmISA
 {
-    const int NumMiscRegs = NUM_MISCREGS;
-
-    static inline std::string getMiscRegName(RegIndex)
+    static inline std::string
+    getMiscRegName(RegIndex)
     {
         return "";
     }
diff --git a/src/arch/arm/regfile.cc b/src/arch/arm/regfile.cc
deleted file mode 100644
index 6bc694050..000000000
--- a/src/arch/arm/regfile.cc
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#include "arch/arm/regfile.hh"
-#include "base/misc.hh"
-#include "sim/serialize.hh"
-
-using namespace std;
-
-namespace ArmISA
-{
-
-void
-copyRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Regs Not Implemented Yet\n");
-}
-
-void
-copyMiscRegs(ThreadContext *src, ThreadContext *dest)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-void
-MiscRegFile::copyMiscRegs(ThreadContext *tc)
-{
-    panic("Copy Misc. Regs Not Implemented Yet\n");
-}
-
-} // namespace ArmISA
diff --git a/src/arch/arm/regfile.hh b/src/arch/arm/regfile.hh
deleted file mode 100644
index 694351b0f..000000000
--- a/src/arch/arm/regfile.hh
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Stephen Hines
- */
-
-#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__
-#define __ARCH_ARM_REGFILE_REGFILE_HH__
-
-#include "arch/arm/types.hh"
-#include "arch/arm/misc_regfile.hh"
-#include "sim/faults.hh"
-
-class Checkpoint;
-class EventManager;
-class ThreadContext;
-
-namespace ArmISA
-{
-    enum FPControlRegNums {
-       FIR = NumFloatArchRegs,
-       FCCR,
-       FEXR,
-       FENR,
-       FCSR
-    };
-
-    enum FCSRBits {
-        Inexact = 1,
-        Underflow,
-        Overflow,
-        DivideByZero,
-        Invalid,
-        Unimplemented
-    };
-
-    enum FCSRFields {
-        Flag_Field = 1,
-        Enable_Field = 6,
-        Cause_Field = 11
-    };
-
-    enum MiscIntRegNums {
-        zero_reg = NumIntArchRegs,
-        addr_reg,
-
-        rhi,
-        rlo,
-
-        r8_fiq,    /* FIQ mode register bank */
-        r9_fiq,
-        r10_fiq,
-        r11_fiq,
-        r12_fiq,
-
-        r13_fiq,   /* FIQ mode SP and LR */
-        r14_fiq,
-
-        r13_irq,   /* IRQ mode SP and LR */
-        r14_irq,
-
-        r13_svc,   /* SVC mode SP and LR */
-        r14_svc,
-
-        r13_undef, /* UNDEF mode SP and LR */
-        r14_undef,
-
-        r13_abt,   /* ABT mode SP and LR */
-        r14_abt
-    };
-
-    void copyRegs(ThreadContext *src, ThreadContext *dest);
-
-    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
-
-} // namespace ArmISA
-
-#endif
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
new file mode 100644
index 000000000..7f9b6b828
--- /dev/null
+++ b/src/arch/arm/registers.hh
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2007-2008 The Florida State University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Stephen Hines
+ */
+
+#ifndef __ARCH_ARM_REGISTERS_HH__
+#define __ARCH_ARM_REGISTERS_HH__
+
+#include "arch/arm/max_inst_regs.hh"
+#include "arch/arm/miscregs.hh"
+
+namespace ArmISA {
+
+using ArmISAInst::MaxInstSrcRegs;
+using ArmISAInst::MaxInstDestRegs;
+
+typedef uint8_t  RegIndex;
+
+typedef uint64_t IntReg;
+
+// floating point register file entry type
+typedef uint32_t FloatRegBits;
+typedef float FloatReg;
+
+// cop-0/cop-1 system control register
+typedef uint64_t MiscReg;
+
+// Constants Related to the number of registers
+const int NumIntArchRegs = 16;
+const int NumIntSpecialRegs = 19;
+const int NumFloatArchRegs = 16;
+const int NumFloatSpecialRegs = 5;
+const int NumInternalProcRegs = 0;
+
+const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs;
+const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;
+
+const int NumMiscRegs = NUM_MISCREGS;
+
+
+// semantically meaningful register indices
+const int ReturnValueReg = 0;
+const int ReturnValueReg1 = 1;
+const int ReturnValueReg2 = 2;
+const int ArgumentReg0 = 0;
+const int ArgumentReg1 = 1;
+const int ArgumentReg2 = 2;
+const int ArgumentReg3 = 3;
+const int FramePointerReg = 11;
+const int StackPointerReg = 13;
+const int ReturnAddressReg = 14;
+const int PCReg = 15;
+
+const int ZeroReg = NumIntArchRegs;
+const int AddrReg = ZeroReg + 1; // Used to generate address for uops
+
+const int SyscallNumReg = ReturnValueReg;
+const int SyscallPseudoReturnReg = ReturnValueReg;
+const int SyscallSuccessReg = ReturnValueReg;
+
+// These help enumerate all the registers for dependence tracking.
+const int FP_Base_DepTag = NumIntRegs;
+const int Ctrl_Base_DepTag = FP_Base_DepTag + NumFloatRegs;
+
+typedef union {
+    IntReg   intreg;
+    FloatReg fpreg;
+    MiscReg  ctrlreg;
+} AnyReg;
+
+enum FPControlRegNums {
+   FIR = NumFloatArchRegs,
+   FCCR,
+   FEXR,
+   FENR,
+   FCSR
+};
+
+enum FCSRBits {
+    Inexact = 1,
+    Underflow,
+    Overflow,
+    DivideByZero,
+    Invalid,
+    Unimplemented
+};
+
+enum FCSRFields {
+    Flag_Field = 1,
+    Enable_Field = 6,
+    Cause_Field = 11
+};
+
+enum MiscIntRegNums {
+    zero_reg = NumIntArchRegs,
+    addr_reg,
+
+    rhi,
+    rlo,
+
+    r8_fiq,    /* FIQ mode register bank */
+    r9_fiq,
+    r10_fiq,
+    r11_fiq,
+    r12_fiq,
+
+    r13_fiq,   /* FIQ mode SP and LR */
+    r14_fiq,
+
+    r13_irq,   /* IRQ mode SP and LR */
+    r14_irq,
+
+    r13_svc,   /* SVC mode SP and LR */
+    r14_svc,
+
+    r13_undef, /* UNDEF mode SP and LR */
+    r14_undef,
+
+    r13_abt,   /* ABT mode SP and LR */
+    r14_abt
+};
+
+} // namespace ArmISA
+
+#endif
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 82d1c332c..2c4e1291c 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -113,25 +113,9 @@ namespace ArmISA
         ROR
     };
 
-    typedef uint8_t  RegIndex;
-
-    typedef uint64_t IntReg;
     typedef uint64_t LargestRead;
     // Need to use 64 bits to make sure that read requests get handled properly
 
-    // floating point register file entry type
-    typedef uint32_t FloatRegBits;
-    typedef float FloatReg;
-
-    // cop-0/cop-1 system control register
-    typedef uint64_t MiscReg;
-
-    typedef union {
-        IntReg   intreg;
-        FloatReg fpreg;
-        MiscReg  ctrlreg;
-    } AnyReg;
-
     typedef int RegContextParam;
     typedef int RegContextVal;
 
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 93f207ec7..a2f0ef170 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -113,6 +113,18 @@ namespace ArmISA {
     {
         return NoFault;
     }
+
+    static inline void
+    copyRegs(ThreadContext *src, ThreadContext *dest)
+    {
+        panic("Copy Regs Not Implemented Yet\n");
+    }
+
+    static inline void
+    copyMiscRegs(ThreadContext *src, ThreadContext *dest)
+    {
+        panic("Copy Misc. Regs Not Implemented Yet\n");
+    }
 };