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authorMatt Horsnell <Matt.Horsnell@arm.com>2011-02-23 15:10:49 -0600
committerMatt Horsnell <Matt.Horsnell@arm.com>2011-02-23 15:10:49 -0600
commitbb319a589e72c006269d6f82fdfa715cc3a6caaf (patch)
tree4a79a01fb6a2013d16d2ff34a140224dd06af9b7 /src/arch/arm
parent7391ea6de63578722d97c9169e60db5b06754137 (diff)
downloadgem5-bb319a589e72c006269d6f82fdfa715cc3a6caaf.tar.xz
ARM: Mark store conditionals as such.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/insts/str.isa9
-rw-r--r--src/arch/arm/isa/insts/swap.isa13
2 files changed, 13 insertions, 9 deletions
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index c26488eba..f661961f7 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -47,7 +47,8 @@ let {{
execBase = 'Store'
def __init__(self, mnem, post, add, writeback, size=4,
- sign=False, user=False, flavor="normal"):
+ sign=False, user=False, flavor="normal",
+ instFlags = []):
super(StoreInst, self).__init__()
self.name = mnem
@@ -58,7 +59,7 @@ let {{
self.sign = sign
self.user = user
self.flavor = flavor
-
+ self.instFlags = instFlags
if self.add:
self.op = " +"
else:
@@ -76,7 +77,7 @@ let {{
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- self.memFlags, [], base, wbDecl)
+ self.memFlags, self.instFlags, base, wbDecl)
header_output += newHeader
decoder_output += newDecoder
@@ -221,6 +222,7 @@ let {{
decConstBase = 'StoreExImm'
basePrefix = 'MemoryExImm'
nameFunc = staticmethod(storeImmClassName)
+ instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreImmEx, self).__init__(*args, **kargs)
@@ -300,6 +302,7 @@ let {{
decConstBase = 'StoreExDImm'
basePrefix = 'MemoryExDImm'
nameFunc = staticmethod(storeDoubleImmClassName)
+ instFlags = ['IsStoreConditional']
def __init__(self, *args, **kargs):
super(StoreDoubleImmEx, self).__init__(*args, **kargs)
diff --git a/src/arch/arm/isa/insts/swap.isa b/src/arch/arm/isa/insts/swap.isa
index d924f3029..6a6ac837c 100644
--- a/src/arch/arm/isa/insts/swap.isa
+++ b/src/arch/arm/isa/insts/swap.isa
@@ -46,7 +46,7 @@ let {{
decConstBase = 'Swap'
def __init__(self, name, Name, eaCode,
- preAccCode, postAccCode, memFlags):
+ preAccCode, postAccCode, memFlags, instFlags = []):
super(SwapInst, self).__init__()
self.name = name
self.Name = Name
@@ -54,6 +54,7 @@ let {{
self.preAccCode = preAccCode
self.postAccCode = postAccCode
self.memFlags = memFlags
+ self.instFlags = instFlags
def emit(self):
global header_output, decoder_output, exec_output
@@ -61,12 +62,10 @@ let {{
"preacc_code": self.preAccCode,
"postacc_code": self.postAccCode }
codeBlobs["predicate_test"] = pickPredicate(codeBlobs)
-
(newHeader,
newDecoder,
newExec) = self.fillTemplates(self.name, self.Name, codeBlobs,
- self.memFlags,
- ['IsStoreConditional'],
+ self.memFlags, self.instFlags,
base = 'Swap')
header_output += newHeader
decoder_output += newDecoder
@@ -77,12 +76,14 @@ let {{
'Dest = cSwap((uint32_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignWord',
- 'ArmISA::TLB::MustBeOne']).emit()
+ 'ArmISA::TLB::MustBeOne'],
+ ['IsStoreConditional']).emit()
SwapInst('swpb', 'Swpb', 'EA = Base;',
'Mem.ub = cSwap(Op1.ub, ((CPSR)Cpsr).e);',
'Dest.ub = cSwap((uint8_t)memData, ((CPSR)Cpsr).e);',
['Request::MEM_SWAP',
'ArmISA::TLB::AlignByte',
- 'ArmISA::TLB::MustBeOne']).emit()
+ 'ArmISA::TLB::MustBeOne'],
+ ['IsStoreConditional']).emit()
}};