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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
commitd70c31437ab4309ba317c90189f1683c8e9e2730 (patch)
tree6fb4ffe1c2e1751fcdd3e4c74cc2df5044aa3f74 /src/arch/arm
parente32aaefe8c8e7125432d8bce45c8428661941cde (diff)
downloadgem5-d70c31437ab4309ba317c90189f1683c8e9e2730.tar.xz
ARM: Support instructions that set the GE bits when they write the condition codes.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/insts/data.isa10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 9de42807e..5d14f3b75 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -43,6 +43,10 @@ let {{
decoder_output = ""
exec_output = ""
+ calcGECode = '''
+ CondCodes = insertBits(CondCodes, 19, 16, resTemp);
+ '''
+
calcQCode = '''
CondCodes = CondCodes | ((resTemp & 1) << 27);
'''
@@ -108,6 +112,8 @@ let {{
negBit = 63
if flagType == "saturate":
immCcCode = calcQCode
+ elif flagType == "ge":
+ immCcCode = calcGECode
else:
immCcCode = calcCcCode % {
"icValue": secondOpRe.sub(immOp2, cCode[0]),
@@ -143,6 +149,8 @@ let {{
negBit = 63
if flagType == "saturate":
regCcCode = calcQCode
+ elif flagType == "ge":
+ immCcCode = calcGECode
else:
regCcCode = calcCcCode % {
"icValue": secondOpRe.sub(regOp2, cCode[1]),
@@ -179,6 +187,8 @@ let {{
negBit = 63
if flagType == "saturate":
regRegCcCode = calcQCode
+ elif flagType == "ge":
+ immCcCode = calcGECode
else:
regRegCcCode = calcCcCode % {
"icValue": secondOpRe.sub(regRegOp2, cCode[2]),