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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:16 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:16 -0500
commite9c8f68c0fcfb72934b852a61671fb94a1927e1d (patch)
tree25c89e490c733f3a3afdd775f2c7a094a69fe4a1 /src/arch/arm
parent05bd3eb4ec3d9fea3dbc46112a47459085d3011c (diff)
downloadgem5-e9c8f68c0fcfb72934b852a61671fb94a1927e1d.tar.xz
ARM: Make undefined instructions obey predication.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/insts/misc.cc8
-rw-r--r--src/arch/arm/insts/misc.hh11
-rw-r--r--src/arch/arm/isa/formats/unknown.isa52
-rw-r--r--src/arch/arm/isa/insts/misc.isa13
4 files changed, 32 insertions, 52 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 0eae37de0..a0af4fc2f 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -261,3 +261,11 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
printReg(ss, op1);
return ss.str();
}
+
+std::string
+UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+{
+ return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
+ "unknown", machInst, machInst.opcode,
+ inst2string(machInst));
+}
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 6d78b311a..c9e114f85 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -258,4 +258,15 @@ class RegImmRegShiftOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
+class UnknownOp : public PredOp
+{
+ protected:
+
+ UnknownOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+ PredOp(mnem, _machInst, __opClass)
+ {}
+
+ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+};
+
#endif
diff --git a/src/arch/arm/isa/formats/unknown.isa b/src/arch/arm/isa/formats/unknown.isa
index e4bb94899..907703015 100644
--- a/src/arch/arm/isa/formats/unknown.isa
+++ b/src/arch/arm/isa/formats/unknown.isa
@@ -40,58 +40,6 @@
//
// Authors: Stephen Hines
-////////////////////////////////////////////////////////////////////
-//
-// Unknown instructions
-//
-
-output header {{
- /**
- * Static instruction class for unknown (illegal) instructions.
- * These cause simulator termination if they are executed in a
- * non-speculative mode. This is a leaf class.
- */
- class Unknown : public ArmStaticInst
- {
- public:
- /// Constructor
- Unknown(ExtMachInst _machInst)
- : ArmStaticInst("unknown", _machInst, No_OpClass)
- {
- // don't call execute() (which panics) if we're on a
- // speculative path
- flags[IsNonSpeculative] = true;
- }
-
- %(BasicExecDeclare)s
-
- std::string
- generateDisassembly(Addr pc, const SymbolTable *symtab) const;
- };
-}};
-
-output decoder {{
- std::string
- Unknown::generateDisassembly(Addr pc, const SymbolTable *symtab) const
- {
- return csprintf("%-10s (inst 0x%x, opcode 0x%x, binary:%s)",
- "unknown", machInst, OPCODE, inst2string(machInst));
- }
-}};
-
-output exec {{
- Fault
- Unknown::execute(%(CPU_exec_context)s *xc,
- Trace::InstRecord *traceData) const
- {
-#if FULL_SYSTEM
- return new UndefinedInstruction;
-#else
- return new UndefinedInstruction(machInst, true);
-#endif
- }
-}};
-
def format Unknown() {{
decode_block = 'return new Unknown(machInst);\n'
}};
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index ee6330f48..ddf548a19 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -468,6 +468,19 @@ let {{
header_output += BasicDeclare.subst(itIop)
decoder_output += BasicConstructor.subst(itIop)
exec_output += PredOpExecute.subst(itIop)
+ unknownCode = '''
+#if FULL_SYSTEM
+ return new UndefinedInstruction;
+#else
+ return new UndefinedInstruction(machInst, true);
+#endif
+ '''
+ unknownIop = InstObjParams("unknown", "Unknown", "UnknownOp", \
+ { "code": unknownCode,
+ "predicate_test": predicateTest })
+ header_output += BasicDeclare.subst(unknownIop)
+ decoder_output += BasicConstructor.subst(unknownIop)
+ exec_output += PredOpExecute.subst(unknownIop)
ubfxCode = '''
Dest = bits(Op1, imm2, imm1);