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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-18 10:50:21 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-19 15:44:07 +0000 |
| commit | 075b8ea6e8f113f58a534834fea7e85a49fdc18d (patch) | |
| tree | f53046d4d26793eb2525d2d6bf2d5f210fa8e30b /src/arch/arm | |
| parent | 373698140d9ee9a24fbee93e8abc55e2809441e3 (diff) | |
| download | gem5-075b8ea6e8f113f58a534834fea7e85a49fdc18d.tar.xz | |
arch-arm: Add HPD bit for TCR_EL2/EL3
This is controlling Hierarchical Permissions for EL3 and for EL2 when
HCR_EL2.E2H = 0.
Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/miscregs_types.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh index 0a9621634..c0eafdaac 100644 --- a/src/arch/arm/miscregs_types.hh +++ b/src/arch/arm/miscregs_types.hh @@ -502,6 +502,7 @@ namespace ArmISA Bitfield<21, 16> t1sz; // EL1 Bitfield<22> a1; // EL1 Bitfield<23> epd1; // EL1 + Bitfield<24> hpd; // EL2/EL3, E2H=0 Bitfield<25, 24> irgn1; // EL1 Bitfield<27, 26> orgn1; // EL1 Bitfield<29, 28> sh1; // EL1 |