arch: Stop using TheISA within the ISAs.

We know for sure what the ISA is, so there's no need for the
indirection.

Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

14 files changed, 54 insertions, 54 deletions

diff --git a/src/arch/arm/isa/insts/fp64.isa b/src/arch/arm/isa/insts/fp64.isa
index 26803e7e5..7decbac25 100644
--- a/src/arch/arm/isa/insts/fp64.isa
+++ b/src/arch/arm/isa/insts/fp64.isa
@@ -45,7 +45,7 @@ let {{
     exec_output = ""
 
     zeroSveVecRegUpperPartCode = '''
-        TheISA::ISA::zeroSveVecRegUpperPart(%s,
+        ArmISA::ISA::zeroSveVecRegUpperPart(%s,
             ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
     '''
 
diff --git a/src/arch/arm/isa/insts/ldr64.isa b/src/arch/arm/isa/insts/ldr64.isa
index fe7eaf0f8..56112a7c1 100644
--- a/src/arch/arm/isa/insts/ldr64.isa
+++ b/src/arch/arm/isa/insts/ldr64.isa
@@ -185,7 +185,7 @@ let {{
                 accCode = 'uint64_t temp M5_VAR_USED = Mem%s;'
             elif self.flavor == "fp":
                 accEpilogCode = '''
-                    TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+                    ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
                         ArmStaticInst::getCurSveVecLen<uint64_t>(
                             xc->tcBase()));
                 '''
@@ -239,10 +239,10 @@ let {{
             # Code that actually handles the access
             if self.flavor == "fp":
                 accEpilogCode = '''
-                    TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
+                    ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest,
                         ArmStaticInst::getCurSveVecLen<uint64_t>(
                             xc->tcBase()));
-                    TheISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
+                    ArmISA::ISA::zeroSveVecRegUpperPart(AA64FpDest2,
                         ArmStaticInst::getCurSveVecLen<uint64_t>(
                             xc->tcBase()));
                 '''
diff --git a/src/arch/arm/isa/insts/neon64_mem.isa b/src/arch/arm/isa/insts/neon64_mem.isa
index 8f53369e9..03ad29409 100644
--- a/src/arch/arm/isa/insts/neon64_mem.isa
+++ b/src/arch/arm/isa/insts/neon64_mem.isa
@@ -45,7 +45,7 @@ let {{
     exec_output = ''
 
     zeroSveVecRegUpperPartCode = '''
-        TheISA::ISA::zeroSveVecRegUpperPart(%s,
+        ArmISA::ISA::zeroSveVecRegUpperPart(%s,
             ArmStaticInst::getCurSveVecLen<uint64_t>(xc->tcBase()));
     '''
 
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index e5e9e2450..c46a34da4 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -1555,7 +1555,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -1616,7 +1616,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto tmpVec = tmpVecC.as<Element>();
         int ePow2Count = 1;
         while (ePow2Count < eCount) {
@@ -1761,7 +1761,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp2 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; i++) {
             auxOp2[i] = AA64FpOp2_ud[i];
@@ -1917,7 +1917,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; i++) {
             auxGpOp[i] = GpOp_x[i];
@@ -1981,7 +1981,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto tmpPred = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             tmpPred[i] = GpOp_x[i];
@@ -2140,7 +2140,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto tmpPred = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             tmpPred[i] = GpOp_x[i];
@@ -2185,7 +2185,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto tmpPred = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             tmpPred[i] = GpOp_x[i];
@@ -2268,7 +2268,7 @@ let {{
         unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
                 xc->tcBase());
         bool dobreak = false;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxGpOp[i] = GpOp_ub[i];
@@ -2320,7 +2320,7 @@ let {{
         unsigned eCount = ArmStaticInst::getCurSveVecLen<uint8_t>(
                 xc->tcBase());
         bool last = POp1_ub.lastActive(GpOp_ub, eCount);
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxGpOp[i] = GpOp_ub[i];
@@ -2458,7 +2458,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxGpOp[i] = GpOp_x[i];
@@ -2500,7 +2500,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxGpOp = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i)
             auxGpOp[i] = GpOp_x[i];
@@ -2568,14 +2568,14 @@ let {{
         if unpackHalf == Unpack.Low:
             if regType == SrcRegType.Predicate:
                 code += '''
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPOp1 = tmpPredC.as<SElement>();
         for (int i = 0; i < eCount; ++i) {
             auxPOp1[i] = POp1_xs[i];
         }'''
             else:
                 code += '''
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<SElement>();
         for (int i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_xs[i];
@@ -2636,7 +2636,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -2707,7 +2707,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxOp1 = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -2736,7 +2736,7 @@ let {{
         code = sveEnabledCheckCode + '''
         unsigned eCount = ArmStaticInst::getCurSveVecLen<Element>(
                 xc->tcBase());
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         int firstelem = -1, lastelem = -2;
         for (int i = 0; i < eCount; ++i) {
@@ -2799,7 +2799,7 @@ let {{
                 xc->tcBase());'''
         if srcType == SrcRegType.Predicate:
             code += '''
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPOp1 = tmpPredC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             uint8_t v = POp1_x.get_raw(i);
@@ -2808,7 +2808,7 @@ let {{
         PDest_x[0] = 0;'''
         else:
             code += '''
-        TheISA::VecRegContainer tmpRegC;
+        ArmISA::VecRegContainer tmpRegC;
         auto auxOp1 = tmpRegC.as<Element>();
         for (unsigned i = 0; i < eCount; ++i) {
             auxOp1[i] = AA64FpOp1_x[i];
@@ -4464,7 +4464,7 @@ let {{
         constexpr unsigned sz = sizeof(Element);
         int s;
         int part = %d;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPDest = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = 2 * i + part;
@@ -4485,7 +4485,7 @@ let {{
     trnIterCode = '''
         int s;
         int part = %d;
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = 2 * i + part;
@@ -4681,7 +4681,7 @@ let {{
         constexpr unsigned sz = sizeof(Element);
         int s;
         int part = %d;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPDest = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount; i++) {
             s = 2 * i + part;
@@ -4705,7 +4705,7 @@ let {{
     uzpIterCode = '''
         int s;
         int part = %d;
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount; i++) {
             s = 2 * i + part;
@@ -4766,7 +4766,7 @@ let {{
         constexpr unsigned sz = sizeof(Element);
         int s;
         int part = %d;
-        TheISA::VecPredRegContainer tmpPredC;
+        ArmISA::VecPredRegContainer tmpPredC;
         auto auxPDest = tmpPredC.as<uint8_t>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = i + (part * (eCount / 2));
@@ -4787,7 +4787,7 @@ let {{
     zipIterCode = '''
         int s;
         int part = %d;
-        TheISA::VecRegContainer tmpVecC;
+        ArmISA::VecRegContainer tmpVecC;
         auto auxDest = tmpVecC.as<Element>();
         for (unsigned i = 0; i < eCount / 2; i++) {
             s = i + (part * (eCount / 2));
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 0f656dac9..0a0469acc 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -51,12 +51,12 @@ def operand_types {{
     'tud' : 'std::array<uint64_t, 2>',
     'sf' : 'float',
     'df' : 'double',
-    'vc' : 'TheISA::VecRegContainer',
+    'vc' : 'ArmISA::VecRegContainer',
     # For operations that are implemented as a template
     'x' : 'TPElem',
     'xs' : 'TPSElem',
     'xd' : 'TPDElem',
-    'pc' : 'TheISA::VecPredRegContainer',
+    'pc' : 'ArmISA::VecPredRegContainer',
     'pb' : 'uint8_t'
 }};
 
diff --git a/src/arch/arm/tracers/tarmac_base.cc b/src/arch/arm/tracers/tarmac_base.cc
index 79e951ab5..3b6201def 100644
--- a/src/arch/arm/tracers/tarmac_base.cc
+++ b/src/arch/arm/tracers/tarmac_base.cc
@@ -47,7 +47,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
 
-using namespace TheISA;
+using namespace ArmISA;
 
 namespace Trace {
 
diff --git a/src/arch/arm/tracers/tarmac_base.hh b/src/arch/arm/tracers/tarmac_base.hh
index 7dab87b43..4e6cbe0f3 100644
--- a/src/arch/arm/tracers/tarmac_base.hh
+++ b/src/arch/arm/tracers/tarmac_base.hh
@@ -85,7 +85,7 @@ class TarmacBaseRecord : public InstRecord
     {
         InstEntry() = default;
         InstEntry(ThreadContext* thread,
-                  TheISA::PCState pc,
+                  ArmISA::PCState pc,
                   const StaticInstPtr staticInst,
                   bool predicate);
 
@@ -101,7 +101,7 @@ class TarmacBaseRecord : public InstRecord
     struct RegEntry
     {
         RegEntry() = default;
-        RegEntry(TheISA::PCState pc);
+        RegEntry(ArmISA::PCState pc);
 
         RegType type;
         RegIndex index;
@@ -123,7 +123,7 @@ class TarmacBaseRecord : public InstRecord
 
   public:
     TarmacBaseRecord(Tick _when, ThreadContext *_thread,
-                     const StaticInstPtr _staticInst, TheISA::PCState _pc,
+                     const StaticInstPtr _staticInst, ArmISA::PCState _pc,
                      const StaticInstPtr _macroStaticInst = NULL);
 
     virtual void dump() = 0;
@@ -135,7 +135,7 @@ class TarmacBaseRecord : public InstRecord
      * @param pc program counter (PCState) variable
      * @return Instruction Set State for the given PCState
      */
-    static ISetState pcToISetState(TheISA::PCState pc);
+    static ISetState pcToISetState(ArmISA::PCState pc);
 };
 
 
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index 860bb1b0b..04a2a051e 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -57,7 +57,7 @@
 #include "sim/sim_exit.hh"
 
 using namespace std;
-using namespace TheISA;
+using namespace ArmISA;
 
 namespace Trace {
 
@@ -743,7 +743,7 @@ TarmacParserRecord::TarmacParserRecordEvent::description() const
 
 void
 TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
-                                        TheISA::PCState pc)
+                                        ArmISA::PCState pc)
 {
     ostream &outs = Trace::output();
     outs << "\nMismatch between gem5 and TARMAC trace @ " << dec << curTick()
@@ -776,8 +776,8 @@ TarmacParserRecord::dump()
     // By default TARMAC splits memory accesses into 4-byte chunks (see
     // 'loadstore-display-width' option in TARMAC plugin)
     uint32_t written_data = 0;
-    unsigned mem_flags = TheISA::TLB::MustBeOne | 3 |
-        TheISA::TLB::AllowUnaligned;
+    unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 |
+        ArmISA::TLB::AllowUnaligned;
 
     ISetState isetstate;
 
@@ -1051,7 +1051,7 @@ TarmacParserRecord::readMemNoEffect(Addr addr, uint8_t *data, unsigned size,
                                     unsigned flags)
 {
     const RequestPtr &req = memReq;
-    TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+    ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
 
     req->setVirt(0, addr, size, flags, thread->pcState().instAddr(),
                  Request::funcMasterId);
diff --git a/src/arch/arm/tracers/tarmac_parser.hh b/src/arch/arm/tracers/tarmac_parser.hh
index 6acdd627e..afba50fef 100644
--- a/src/arch/arm/tracers/tarmac_parser.hh
+++ b/src/arch/arm/tracers/tarmac_parser.hh
@@ -83,7 +83,7 @@ class TarmacParserRecord : public TarmacBaseRecord
         /** Current instruction. */
         const StaticInstPtr inst;
         /** PC of the current instruction. */
-        TheISA::PCState pc;
+        ArmISA::PCState pc;
         /** True if a mismatch has been detected for this instruction. */
         bool mismatch;
         /**
@@ -95,7 +95,7 @@ class TarmacParserRecord : public TarmacBaseRecord
         TarmacParserRecordEvent(TarmacParser& _parent,
                                 ThreadContext *_thread,
                                 const StaticInstPtr _inst,
-                                TheISA::PCState _pc,
+                                ArmISA::PCState _pc,
                                 bool _mismatch,
                                 bool _mismatch_on_pc_or_opcode) :
             parent(_parent), thread(_thread), inst(_inst), pc(_pc),
@@ -130,10 +130,10 @@ class TarmacParserRecord : public TarmacBaseRecord
      * by gem5.
      */
     static void printMismatchHeader(const StaticInstPtr inst,
-                                    TheISA::PCState pc);
+                                    ArmISA::PCState pc);
 
     TarmacParserRecord(Tick _when, ThreadContext *_thread,
-                       const StaticInstPtr _staticInst, TheISA::PCState _pc,
+                       const StaticInstPtr _staticInst, ArmISA::PCState _pc,
                        TarmacParser& _parent,
                        const StaticInstPtr _macroStaticInst = NULL);
 
@@ -241,7 +241,7 @@ class TarmacParser : public InstTracer
 
     InstRecord *
     getInstRecord(Tick when, ThreadContext *tc, const StaticInstPtr staticInst,
-                  TheISA::PCState pc,
+                  ArmISA::PCState pc,
                   const StaticInstPtr macroStaticInst = NULL)
     {
         if (!started && pc.pc() == startPc)
diff --git a/src/arch/arm/tracers/tarmac_record.hh b/src/arch/arm/tracers/tarmac_record.hh
index f54abf56a..d2534732c 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -178,7 +178,7 @@ class TarmacTracerRecord : public TarmacBaseRecord
 
   public:
     TarmacTracerRecord(Tick _when, ThreadContext *_thread,
-                       const StaticInstPtr _staticInst, TheISA::PCState _pc,
+                       const StaticInstPtr _staticInst, ArmISA::PCState _pc,
                        TarmacTracer& _tracer,
                        const StaticInstPtr _macroStaticInst = NULL);
 
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index dea040992..90f1a6fc3 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -56,7 +56,7 @@ TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(
     const auto thread = tarmCtx.thread;
 
     // Evaluate physical address
-    TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+    ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
     paddrValid = dtb->translateFunctional(thread, addr, paddr);
 }
 
@@ -70,7 +70,7 @@ TarmacTracerRecordV8::TraceMemEntryV8::TraceMemEntryV8(
     const auto thread = tarmCtx.thread;
 
     // Evaluate physical address
-    TheISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
+    ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
     dtb->translateFunctional(thread, addr, paddr);
 }
 
diff --git a/src/arch/arm/tracers/tarmac_record_v8.hh b/src/arch/arm/tracers/tarmac_record_v8.hh
index adf638f99..a727ea6a6 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.hh
+++ b/src/arch/arm/tracers/tarmac_record_v8.hh
@@ -130,7 +130,7 @@ class TarmacTracerRecordV8 : public TarmacTracerRecord
 
   public:
     TarmacTracerRecordV8(Tick _when, ThreadContext *_thread,
-                         const StaticInstPtr _staticInst, TheISA::PCState _pc,
+                         const StaticInstPtr _staticInst, ArmISA::PCState _pc,
                          TarmacTracer& _parent,
                          const StaticInstPtr _macroStaticInst = NULL)
       : TarmacTracerRecord(_when, _thread, _staticInst, _pc,
diff --git a/src/arch/arm/tracers/tarmac_tracer.cc b/src/arch/arm/tracers/tarmac_tracer.cc
index b6f876de5..41e4e49c4 100644
--- a/src/arch/arm/tracers/tarmac_tracer.cc
+++ b/src/arch/arm/tracers/tarmac_tracer.cc
@@ -75,7 +75,7 @@ TarmacTracer::TarmacTracer(const Params *p)
 InstRecord *
 TarmacTracer::getInstRecord(Tick when, ThreadContext *tc,
                            const StaticInstPtr staticInst,
-                           TheISA::PCState pc,
+                           ArmISA::PCState pc,
                            const StaticInstPtr macroStaticInst)
 {
     // Check if we need to start tracing since we have passed the
diff --git a/src/arch/arm/tracers/tarmac_tracer.hh b/src/arch/arm/tracers/tarmac_tracer.hh
index 78739999d..58a47d175 100644
--- a/src/arch/arm/tracers/tarmac_tracer.hh
+++ b/src/arch/arm/tracers/tarmac_tracer.hh
@@ -63,7 +63,7 @@ class TarmacContext
   public:
     TarmacContext(ThreadContext* _thread,
                   const StaticInstPtr _staticInst,
-                  TheISA::PCState _pc)
+                  ArmISA::PCState _pc)
       : thread(_thread), staticInst(_staticInst), pc(_pc)
     {}
 
@@ -72,7 +72,7 @@ class TarmacContext
   public:
     ThreadContext* thread;
     const StaticInstPtr staticInst;
-    TheISA::PCState pc;
+    ArmISA::PCState pc;
 };
 
 /**
@@ -99,7 +99,7 @@ class TarmacTracer : public InstTracer
      */
     InstRecord* getInstRecord(Tick when, ThreadContext *tc,
                               const StaticInstPtr staticInst,
-                              TheISA::PCState pc,
+                              ArmISA::PCState pc,
                               const StaticInstPtr macroStaticInst = NULL);
 
   protected: