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| author | Gabe Black <gabeblack@google.com> | 2019-11-05 15:48:48 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-12-27 20:52:13 +0000 |
| commit | 1a71417b89f20f5637f60b6a032f8ba9cfc95378 (patch) | |
| tree | bc07d99649a3396a5408eebf458a17df59dc0d55 /src/arch/arm | |
| parent | eec8ac1595320cf40650f3c03f05248015dd17ae (diff) | |
| download | gem5-1a71417b89f20f5637f60b6a032f8ba9cfc95378.tar.xz | |
fastmodel: Handle "special" vector regs without calling into IRIS.
These registers don't have an architectural equivalent, but they may
need to be accessed by generic code, for instance the code that
checkpoints a thread context.
Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/fastmodel/iris/arm/thread_context.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc index c48ade817..4ef879488 100644 --- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc @@ -190,6 +190,11 @@ const ArmISA::VecRegContainer & ArmThreadContext::readVecReg(const RegId ®_id) const { const RegIndex idx = reg_id.index(); + // Ignore accesses to registers which aren't architected. gem5 defines a + // few extra registers which it uses internally in the implementation of + // some instructions. + if (idx >= vecRegIds.size()) + return vecRegs.at(idx); ArmISA::VecRegContainer ® = vecRegs.at(idx); iris::ResourceReadResult result; |