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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-26 09:55:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 22273000d0cd8b695c4dea9613c649f764ed94ea (patch) | |
| tree | 12bb8ae66fb688e4b3a0663e55912d5dd579e9cc /src/arch/arm | |
| parent | 1e1d5e247ecc55dc3d92875ca5ec6ae70879d8c1 (diff) | |
| download | gem5-22273000d0cd8b695c4dea9613c649f764ed94ea.tar.xz | |
arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 76a991746..5f45916b6 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4616,7 +4616,7 @@ ISA::initializeMiscRegMetadata() .secure().exceptUserMode() .mapsTo(MISCREG_ICC_BPR1_S); InitReg(MISCREG_ICC_CTLR_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_CTLR); InitReg(MISCREG_ICC_CTLR_EL1_NS) .bankedChild() |