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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-23 15:56:32 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 20:00:34 +0000 |
| commit | 34f1b771ed911ac8dc9f02ded63add7de3c263ed (patch) | |
| tree | 3c504926f9c8253c47a3af43d7c84f3a14193c45 /src/arch/arm | |
| parent | 22273000d0cd8b695c4dea9613c649f764ed94ea (diff) | |
| download | gem5-34f1b771ed911ac8dc9f02ded63add7de3c263ed.tar.xz | |
arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 5f45916b6..81bc3efae 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -4533,7 +4533,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP0R3); InitReg(MISCREG_ICC_AP1R0_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R0); InitReg(MISCREG_ICC_AP1R0_EL1_NS) .bankedChild() @@ -4544,7 +4544,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP1R0_S); InitReg(MISCREG_ICC_AP1R1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R1); InitReg(MISCREG_ICC_AP1R1_EL1_NS) .bankedChild() @@ -4555,7 +4555,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP1R1_S); InitReg(MISCREG_ICC_AP1R2_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R2); InitReg(MISCREG_ICC_AP1R2_EL1_NS) .bankedChild() @@ -4566,7 +4566,7 @@ ISA::initializeMiscRegMetadata() .allPrivileges().exceptUserMode() .mapsTo(MISCREG_ICC_AP1R2_S); InitReg(MISCREG_ICC_AP1R3_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_AP1R3); InitReg(MISCREG_ICC_AP1R3_EL1_NS) .bankedChild() |