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| author | Ciro Santilli <ciro.santilli@arm.com> | 2019-08-28 16:03:33 +0100 |
|---|---|---|
| committer | Ciro Santilli <ciro.santilli@arm.com> | 2019-09-06 15:00:35 +0000 |
| commit | 36a575071cd460255ca67ec5bdd6862d9c164919 (patch) | |
| tree | a6140eca99856141b82b3058ea17a372299f8634 /src/arch/arm | |
| parent | ead1e7a2a36a1d5fd1c612554590c99a05a98ce4 (diff) | |
| download | gem5-36a575071cd460255ca67ec5bdd6862d9c164919.tar.xz | |
arch-arm: fix GDB stub after SVE
The SVE patches made registers longer by increasing NumVecElemPerVecReg,
but the GDB XML was not updated to account for that, and as a result GDB
connections were failing with:
Remote 'g' packet reply is too long
This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD
register sizes to get it back working. SVE GDB support is not added here.
Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/registers.hh | 5 | ||||
| -rw-r--r-- | src/arch/arm/remote_gdb.cc | 6 | ||||
| -rw-r--r-- | src/arch/arm/remote_gdb.hh | 4 |
3 files changed, 9 insertions, 6 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 4a8e960d4..75945ad81 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited + * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -61,6 +61,9 @@ const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + using ArmISAInst::MaxInstDestRegs; using ArmISAInst::MaxMiscDestRegs; +// Number of VecElem per Vector Register considering only pre-SVE +// Advanced SIMD registers. +constexpr unsigned NumVecElemPerNeonVecReg = 4; // Number of VecElem per Vector Register, computed based on the vector length constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords; diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc index 05adfeaed..ceb0ffafe 100644 --- a/src/arch/arm/remote_gdb.cc +++ b/src/arch/arm/remote_gdb.cc @@ -1,7 +1,7 @@ /* * Copyright 2015 LabWare * Copyright 2014 Google Inc. - * Copyright (c) 2010, 2013, 2016, 2018 ARM Limited + * Copyright (c) 2010, 2013, 2016, 2018-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -212,7 +212,7 @@ RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context) size_t base = 0; for (int i = 0; i < NumVecV8ArchRegs; i++) { auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>(); - for (size_t j = 0; j < NumVecElemPerVecReg; j++) { + for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) { r.v[base] = v[j]; base++; } @@ -241,7 +241,7 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const for (int i = 0; i < NumVecV8ArchRegs; i++) { auto v = (context->getWritableVecReg( RegId(VecRegClass, i))).as<VecElem>(); - for (size_t j = 0; j < NumVecElemPerVecReg; j++) { + for (size_t j = 0; j < NumVecElemPerNeonVecReg; j++) { v[j] = r.v[base]; base++; } diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh index 3e4c5ef8d..e52ed663a 100644 --- a/src/arch/arm/remote_gdb.hh +++ b/src/arch/arm/remote_gdb.hh @@ -1,7 +1,7 @@ /* * Copyright 2015 LabWare * Copyright 2014 Google, Inc. - * Copyright (c) 2013, 2016, 2018 ARM Limited + * Copyright (c) 2013, 2016, 2018-2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -97,7 +97,7 @@ class RemoteGDB : public BaseRemoteGDB uint64_t spx; uint64_t pc; uint32_t cpsr; - VecElem v[NumVecV8ArchRegs * NumVecElemPerVecReg]; + VecElem v[NumVecV8ArchRegs * NumVecElemPerNeonVecReg]; uint32_t fpsr; uint32_t fpcr; } M5_ATTR_PACKED r; |