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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-12-10 09:05:43 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:47:58 +0000 |
| commit | 4d44889635fc31886ac993a3b5260afe006bd2a3 (patch) | |
| tree | 1ce40ba34aaeaab5b553119153df6c68f3d186a0 /src/arch/arm | |
| parent | 3ec5afd8d2d5b9457820ef0725997bb40b701c7b (diff) | |
| download | gem5-4d44889635fc31886ac993a3b5260afe006bd2a3.tar.xz | |
arch-arm: Remove unused float operands
Removing FaP1 and FDest2 since they are not currently used by any ARM
instruction.
Change-Id: I4251dfcdd3f4434caaf0bdab507c1c3bd53fb5d2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15596
Reviewed-by: Ciro Santilli <ciro.santilli@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 3daba5739..3c231b9ad 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -192,7 +192,6 @@ def operands {{ 'AIWDest': intRegAIWPC('dest'), 'Dest2': intReg('dest2'), 'XDest2': intRegX64('dest2'), - 'FDest2': floatReg('dest2'), 'IWDest2': intRegIWPC('dest2'), 'Result': intReg('result'), 'XResult': intRegX64('result'), @@ -550,7 +549,6 @@ def operands {{ 'WURa' : intRegW64('ura'), 'IWRa' : intRegIWPC('ura'), 'Fa' : floatReg('ura'), - 'FaP1' : floatReg('ura + 1'), 'URb' : intReg('urb'), 'XURb' : intRegX64('urb'), 'URc' : intReg('urc'), |