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authorGabe Black <gabeblack@google.com>2019-08-28 16:34:46 -0700
committerGabe Black <gabeblack@google.com>2019-10-02 01:27:29 +0000
commit5fdaa0d719cb1d2c6847ff1ee69fa54ceae55172 (patch)
tree61447049f1b5bff57a1387cd27a7d0244f90a82a /src/arch/arm
parent7e1b5bd3bc21a324694e9a892ee6d5219ee7505f (diff)
downloadgem5-5fdaa0d719cb1d2c6847ff1ee69fa54ceae55172.tar.xz
fastmodel: Let the EVS set an attribute for getSendFunctional to return.
The iris CPU model doesn't necessarily know the best way to send functional packets (what port? what type is that port?), but only has a generic sc_module pointer to the EVS and so can't call specialized methods on it. There also isn't any common base class for EVSes to cast into in a generic way. This attribute mechanism lets the EVS set up its own sendFunctional implementation however it needs to using facilities that are built into generic sc_objects. Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/fastmodel/iris/cpu.cc8
-rw-r--r--src/arch/arm/fastmodel/iris/cpu.hh12
2 files changed, 20 insertions, 0 deletions
diff --git a/src/arch/arm/fastmodel/iris/cpu.cc b/src/arch/arm/fastmodel/iris/cpu.cc
index 234a1ca0d..246fe0cf0 100644
--- a/src/arch/arm/fastmodel/iris/cpu.cc
+++ b/src/arch/arm/fastmodel/iris/cpu.cc
@@ -61,6 +61,14 @@ BaseCPU::BaseCPU(BaseCPUParams *params, sc_core::sc_module *_evs) :
panic_if(base && !periodAttribute,
"The EVS clock period attribute is not of type "
"sc_attribute<Tick>.");
+
+ base = evs->get_attribute(SendFunctionalAttributeName);
+ sendFunctional =
+ dynamic_cast<sc_core::sc_attribute<PortProxy::SendFunctionalFunc> *>(
+ base);
+ panic_if(base && !sendFunctional,
+ "The EVS send functional attribute is not of type "
+ "sc_attribute<PortProxy::SendFunctionalFunc>.");
}
BaseCPU::~BaseCPU()
diff --git a/src/arch/arm/fastmodel/iris/cpu.hh b/src/arch/arm/fastmodel/iris/cpu.hh
index c6c75a2ff..f7be5cb76 100644
--- a/src/arch/arm/fastmodel/iris/cpu.hh
+++ b/src/arch/arm/fastmodel/iris/cpu.hh
@@ -49,6 +49,9 @@ static const std::string PeriodAttributeName = "gem5_clock_period_attribute";
// The name of the attribute the subsystem should create which will be set to
// a pointer to its corresponding gem5 CPU.
static const std::string Gem5CpuAttributeName = "gem5_cpu";
+// The name of the attribute the subsystem should create to hold the
+// sendFunctional delegate for port proxies.
+static const std::string SendFunctionalAttributeName = "gem5_send_functional";
// This CPU class adds some mechanisms which help attach the gem5 and fast
// model CPUs to each other. It acts as a base class for the gem5 CPU, and
@@ -83,12 +86,21 @@ class BaseCPU : public ::BaseCPU
Counter totalInsts() const override;
Counter totalOps() const override { return totalInsts(); }
+ PortProxy::SendFunctionalFunc
+ getSendFunctional() override
+ {
+ if (sendFunctional)
+ return sendFunctional->value;
+ return ::BaseCPU::getSendFunctional();
+ }
+
protected:
sc_core::sc_module *evs;
private:
sc_core::sc_event *clockEvent;
sc_core::sc_attribute<Tick> *periodAttribute;
+ sc_core::sc_attribute<PortProxy::SendFunctionalFunc> *sendFunctional;
protected:
void