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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-05 10:52:47 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-19 10:54:14 +0000 |
| commit | 6b6ac525f7bcb4259ef2065919bc9985c48ef35d (patch) | |
| tree | 86987681ecbd6ddb2eb3813f8c610f362eeecad1 /src/arch/arm | |
| parent | ee00675d24761f2df22fa588cba8dee7d1050f3a (diff) | |
| download | gem5-6b6ac525f7bcb4259ef2065919bc9985c48ef35d.tar.xz | |
arch-arm: PSTATE.PAN changes should inval cached regs in TLB
Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/isa.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b95710506..6e65102b6 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -791,6 +791,10 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) getDTBPtr(tc)->invalidateMiscReg(); } + if (cpsr.pan != old_cpsr.pan) { + getDTBPtr(tc)->invalidateMiscReg(); + } + DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); PCState pc = tc->pcState(); |