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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-24 10:10:25 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-24 12:50:03 +0000 |
| commit | 8529cdad6bb6d6aceb2e12e785607f0d409c0d76 (patch) | |
| tree | c83d4c36128643bb38e0c9b0057d000a23f536b4 /src/arch/arm | |
| parent | 32a23114c14cebc5ec0067ac739144b50e412219 (diff) | |
| download | gem5-8529cdad6bb6d6aceb2e12e785607f0d409c0d76.tar.xz | |
arch-arm: Fix fallthrough when trapping at EL2
This had been caused by the introduction of GICv3 registers trapping in
commit 32a23114c14cebc5ec0067ac739144b50e412219
Change-Id: I5073e2891f3ff5c5a9e05d3456dad6f4f8ffba0d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18909
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/insts/misc64.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc index fed2d9ac8..423aaca25 100644 --- a/src/arch/arm/insts/misc64.cc +++ b/src/arch/arm/insts/misc64.cc @@ -269,6 +269,7 @@ MiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, break; case MISCREG_IMPDEF_UNIMPL: trap_to_hyp = hcr.tidcp && el == EL1; + break; // GICv3 regs case MISCREG_ICC_SGI0R_EL1: if (tc->getIsaPtr()->haveGICv3CpuIfc()) |