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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-19 10:20:14 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-23 08:32:25 +0000 |
commit | 92518ec8437b422f86f7c315a83d9c2aa5fdbe1b (patch) | |
tree | f2a9e55d8e8c22bb32bc8fa8df81c97903b5391a /src/arch/arm | |
parent | b8a4c876905d605cf180e77f7d1bb08f2ed22940 (diff) | |
download | gem5-92518ec8437b422f86f7c315a83d9c2aa5fdbe1b.tar.xz |
arch-arm: Change mcrMrc15TrapToHyp signature
This patch is moving MiscRegs reading inside the mcrMrc15TrapToHyp
helper function. Rather than passing registers as arguments,
we are just passing a ThreadContext pointer
Change-Id: I6636dd3a4f92f757479d8a8d2c47de050a0b9eae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17988
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/insts/misc.cc | 18 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 27 | ||||
-rw-r--r-- | src/arch/arm/utility.cc | 9 | ||||
-rw-r--r-- | src/arch/arm/utility.hh | 4 |
4 files changed, 26 insertions, 32 deletions
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc index 8efb81a6c..14b345843 100644 --- a/src/arch/arm/insts/misc.cc +++ b/src/arch/arm/insts/misc.cc @@ -339,15 +339,8 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, Fault McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const { - uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); - uint32_t hcr = xc->readMiscReg(MISCREG_HCR); - uint32_t scr = xc->readMiscReg(MISCREG_SCR); - uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); - uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); - uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); + bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss); - bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, - hcptr, iss); if (hypTrap) { return std::make_shared<HypervisorTrap>(machInst, iss, EC_TRAPPED_CP15_MCR_MRC); @@ -371,15 +364,8 @@ McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic, Fault McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const { - uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); - uint32_t hcr = xc->readMiscReg(MISCREG_HCR); - uint32_t scr = xc->readMiscReg(MISCREG_SCR); - uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); - uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); - uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); + bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss); - bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, - hcptr, iss); if (hypTrap) { return std::make_shared<HypervisorTrap>(machInst, iss, EC_TRAPPED_CP15_MCR_MRC); diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 932deebbf..92a6b53f1 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -920,8 +920,9 @@ let {{ MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(RegId(MiscRegClass, preFlatOp1)).index(); - bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, - Hcptr, imm); + + bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm); + bool can_read, undefined; std::tie(can_read, undefined) = canReadCoprocReg(miscReg, Scr, Cpsr); // if we're in non secure PL1 mode then we can trap regargless of whether @@ -952,8 +953,9 @@ let {{ MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(RegId(MiscRegClass, preFlatDest)).index(); - bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, - Hcptr, imm); + + bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm); + bool can_write, undefined; std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); @@ -1092,8 +1094,9 @@ let {{ int preFlatDest = snsBankedIndex(dest, xc->tcBase()); MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId( RegId(MiscRegClass, preFlatDest)).index(); - bool hypTrap = mcrMrc15TrapToHyp(miscReg, Hcr, Cpsr, Scr, Hdcr, Hstr, - Hcptr, imm); + + bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm); + bool can_write, undefined; std::tie(can_write, undefined) = canWriteCoprocReg(miscReg, Scr, Cpsr); @@ -1190,8 +1193,8 @@ let {{ isbCode = ''' // If the barrier is due to a CP15 access check for hyp traps - if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, Hcr, Cpsr, Scr, - Hdcr, Hstr, Hcptr, imm)) { + if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB, + xc->tcBase(), imm)) { return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } @@ -1206,8 +1209,8 @@ let {{ dsbCode = ''' // If the barrier is due to a CP15 access check for hyp traps - if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, Hcr, Cpsr, Scr, - Hdcr, Hstr, Hcptr, imm)) { + if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB, + xc->tcBase(), imm)) { return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } @@ -1222,8 +1225,8 @@ let {{ dmbCode = ''' // If the barrier is due to a CP15 access check for hyp traps - if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, Hcr, Cpsr, Scr, - Hdcr, Hstr, Hcptr, imm)) { + if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB, + xc->tcBase(), imm)) { return std::make_shared<HypervisorTrap>(machInst, imm, EC_TRAPPED_CP15_MCR_MRC); } diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc index 29b39b89e..b41134f03 100644 --- a/src/arch/arm/utility.cc +++ b/src/arch/arm/utility.cc @@ -461,8 +461,7 @@ roundPage(Addr addr) } bool -mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, - HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss) +mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss) { bool isRead; uint32_t crm; @@ -472,6 +471,12 @@ mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, uint32_t opc2; bool trapToHype = false; + const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); + const HCR hcr = tc->readMiscReg(MISCREG_HCR); + const SCR scr = tc->readMiscReg(MISCREG_SCR); + const HDCR hdcr = tc->readMiscReg(MISCREG_HDCR); + const HSTR hstr = tc->readMiscReg(MISCREG_HSTR); + const HCPTR hcptr = tc->readMiscReg(MISCREG_HCPTR); if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { mcrMrcIssExtract(iss, isRead, crm, rt, crn, opc1, opc2); diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh index c6ff9469d..15daeb8cf 100644 --- a/src/arch/arm/utility.hh +++ b/src/arch/arm/utility.hh @@ -313,8 +313,8 @@ msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn, } bool -mcrMrc15TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, - HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); +mcrMrc15TrapToHyp(const MiscRegIndex miscReg, ThreadContext *tc, uint32_t iss); + bool mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, HDCR hdcr, HSTR hstr, HCPTR hcptr, uint32_t iss); |