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| author | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-02-22 11:29:10 -0500 |
|---|---|---|
| committer | Andrea Mondelli <Andrea.Mondelli@ucf.edu> | 2019-03-01 16:46:47 +0000 |
| commit | 96cc03f90db82fa8f84248ef478362267dba292c (patch) | |
| tree | 973f9dad0038300ba7fd761c3ef2cbfb1e56bf67 /src/arch/arm | |
| parent | a7eebbfa693e3fa55c0a9c876b97adcf72662c71 (diff) | |
| download | gem5-96cc03f90db82fa8f84248ef478362267dba292c.tar.xz | |
mem-cache: alias to mem::getMasterPort in TLB class
TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().
The TLB::getMasterPort() is renamed according to the expected behavior.
Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/tlb.cc | 2 | ||||
| -rw-r--r-- | src/arch/arm/tlb.hh | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 46056d07b..ed7e68039 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1244,7 +1244,7 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc, } BaseMasterPort* -TLB::getMasterPort() +TLB::getTableWalkerMasterPort() { return &stage2Mmu->getPort(); } diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 637240abb..8ca176a82 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -401,7 +401,7 @@ class TLB : public BaseTLB * * @return A pointer to the walker master port */ - BaseMasterPort* getMasterPort() override; + BaseMasterPort* getTableWalkerMasterPort() override; // Caching misc register values here. // Writing to misc registers needs to invalidate them. |