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| author | Ciro Santilli <ciro.santilli@arm.com> | 2019-09-30 16:52:32 +0100 |
|---|---|---|
| committer | Ciro Santilli <ciro.santilli@arm.com> | 2019-10-07 10:26:20 +0000 |
| commit | a00953c0a7c80ac68003546a50b6556975720235 (patch) | |
| tree | b0ee410feb377b08c9d89d0f06a499453345c11e /src/arch/arm | |
| parent | a586380b32a199b40d1f6f5e14ce7731ee5a3c67 (diff) | |
| download | gem5-a00953c0a7c80ac68003546a50b6556975720235.tar.xz | |
kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR
Those registers are 32-bit instead of 64 in the KVM API.
The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains:
0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr
0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr
The register itself is 64-bit in the ARM manual, but the top 32 are
RES0.
This fixes the following error when running ARM KVM early in the
simulation:
panic: KVM: Failed to set register (0x60300000001000d4) value
(errno: 22)
Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/kvm/armv8_cpu.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc index 3757e2602..5a843fcd5 100644 --- a/src/arch/arm/kvm/armv8_cpu.cc +++ b/src/arch/arm/kvm/armv8_cpu.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, 2017 ARM Limited + * Copyright (c) 2015, 2017, 2019 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -109,8 +109,8 @@ const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = { MiscRegInfo(INT_REG(spsr[KVM_SPSR_UND]), MISCREG_SPSR_UND, "SPSR(UND)"), MiscRegInfo(INT_REG(spsr[KVM_SPSR_IRQ]), MISCREG_SPSR_IRQ, "SPSR(IRQ)"), MiscRegInfo(INT_REG(spsr[KVM_SPSR_FIQ]), MISCREG_SPSR_FIQ, "SPSR(FIQ)"), - MiscRegInfo(INT_REG(fp_regs.fpsr), MISCREG_FPSR, "FPSR"), - MiscRegInfo(INT_REG(fp_regs.fpcr), MISCREG_FPCR, "FPCR"), + MiscRegInfo(CORE_REG(fp_regs.fpsr, U32), MISCREG_FPSR, "FPSR"), + MiscRegInfo(CORE_REG(fp_regs.fpcr, U32), MISCREG_FPCR, "FPCR"), }; const std::set<MiscRegIndex> ArmV8KvmCPU::deviceRegSet = { |