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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:06 -0500
commita895514d35d4011f3110ad4d8290287d7b7b6856 (patch)
treea59e6cad220a8bf240d2e27d029b696bac77195f /src/arch/arm
parent3f12eb02ab3dcde6e96e2ae0d50710bf5541ec54 (diff)
downloadgem5-a895514d35d4011f3110ad4d8290287d7b7b6856.tar.xz
ARM: Decode the unsigned 8 and 16 bit add and subtract instructions.
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/isa/formats/data.isa30
1 files changed, 18 insertions, 12 deletions
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 98274e3eb..05d89abf5 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -285,17 +285,17 @@ def format ArmParallelAddSubtract() {{
case 0x1:
switch (op2) {
case 0x0:
- return new WarnUnimplemented("uadd16", machInst);
+ return new Uadd16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x1:
- return new WarnUnimplemented("uasx", machInst);
+ return new UasxRegCc(machInst, rd, rn, rm, 0, LSL);
case 0x2:
- return new WarnUnimplemented("usax", machInst);
+ return new UsaxRegCc(machInst, rd, rn, rm, 0, LSL);
case 0x3:
- return new WarnUnimplemented("usub16", machInst);
+ return new Usub16RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x4:
- return new WarnUnimplemented("uadd8", machInst);
+ return new Uadd8RegCc(machInst, rd, rn, rm, 0, LSL);
case 0x7:
- return new WarnUnimplemented("usub8", machInst);
+ return new Usub8RegCc(machInst, rd, rn, rm, 0, LSL);
}
break;
case 0x2:
@@ -607,17 +607,23 @@ def format Thumb32DataProcReg() {{
case 0x0:
switch (op1) {
case 0x1:
- return new WarnUnimplemented("uadd16", machInst);
+ return new Uadd16RegCc(machInst, rd,
+ rn, rm, 0, LSL);
case 0x2:
- return new WarnUnimplemented("uasx", machInst);
+ return new UasxRegCc(machInst, rd,
+ rn, rm, 0, LSL);
case 0x6:
- return new WarnUnimplemented("usax", machInst);
+ return new UsaxRegCc(machInst, rd,
+ rn, rm, 0, LSL);
case 0x5:
- return new WarnUnimplemented("usub16", machInst);
+ return new Usub16RegCc(machInst, rd,
+ rn, rm, 0, LSL);
case 0x0:
- return new WarnUnimplemented("uadd8", machInst);
+ return new Uadd8RegCc(machInst, rd,
+ rn, rm, 0, LSL);
case 0x4:
- return new WarnUnimplemented("usub8", machInst);
+ return new Usub8RegCc(machInst, rd,
+ rn, rm, 0, LSL);
}
break;
case 0x1: