diff options
author | Gabe Black <gabeblack@google.com> | 2019-09-02 21:26:12 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-10-19 01:45:48 +0000 |
commit | ae390c629f2a10fd6a1c2eb50b7d3510d6e091da (patch) | |
tree | 51f12635838755ef7519bea1c72bfb96e0214336 /src/arch/arm | |
parent | 1c047f8b92f5708bbef50d24cf47902d5da313e3 (diff) | |
download | gem5-ae390c629f2a10fd6a1c2eb50b7d3510d6e091da.tar.xz |
arch: Make a base class for Interrupts.
That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.
Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/ArmInterrupts.py | 4 | ||||
-rw-r--r-- | src/arch/arm/interrupts.hh | 6 | ||||
-rw-r--r-- | src/arch/arm/isa.cc | 27 | ||||
-rw-r--r-- | src/arch/arm/isa/includes.isa | 1 | ||||
-rw-r--r-- | src/arch/arm/isa/insts/misc.isa | 5 |
5 files changed, 28 insertions, 15 deletions
diff --git a/src/arch/arm/ArmInterrupts.py b/src/arch/arm/ArmInterrupts.py index 68a58958d..9a6b546a5 100644 --- a/src/arch/arm/ArmInterrupts.py +++ b/src/arch/arm/ArmInterrupts.py @@ -26,9 +26,9 @@ # # Authors: Ali Saidi -from m5.SimObject import SimObject +from m5.objects.BaseInterrupts import BaseInterrupts -class ArmInterrupts(SimObject): +class ArmInterrupts(BaseInterrupts): type = 'ArmInterrupts' cxx_class = 'ArmISA::Interrupts' cxx_header = "arch/arm/interrupts.hh" diff --git a/src/arch/arm/interrupts.hh b/src/arch/arm/interrupts.hh index 8d0cb49ea..1f8e321cd 100644 --- a/src/arch/arm/interrupts.hh +++ b/src/arch/arm/interrupts.hh @@ -48,15 +48,15 @@ #include "arch/arm/miscregs.hh" #include "arch/arm/registers.hh" #include "arch/arm/utility.hh" +#include "arch/generic/interrupts.hh" #include "cpu/thread_context.hh" #include "debug/Interrupt.hh" #include "params/ArmInterrupts.hh" -#include "sim/sim_object.hh" namespace ArmISA { -class Interrupts : public SimObject +class Interrupts : public BaseInterrupts { private: BaseCPU * cpu; @@ -80,7 +80,7 @@ class Interrupts : public SimObject return dynamic_cast<const Params *>(_params); } - Interrupts(Params * p) : SimObject(p), cpu(NULL) + Interrupts(Params * p) : BaseInterrupts(p), cpu(NULL) { clearAll(); } diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 6e65102b6..712b43040 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -39,6 +39,9 @@ */ #include "arch/arm/isa.hh" + +#include "arch/arm/faults.hh" +#include "arch/arm/interrupts.hh" #include "arch/arm/pmu.hh" #include "arch/arm/system.hh" #include "arch/arm/tlb.hh" @@ -672,15 +675,23 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) case MISCREG_DBGDSCRint: return 0; case MISCREG_ISR: - return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( - readMiscRegNoEffect(MISCREG_HCR), - readMiscRegNoEffect(MISCREG_CPSR), - readMiscRegNoEffect(MISCREG_SCR)); + { + auto ic = dynamic_cast<ArmISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + return ic->getISR( + readMiscRegNoEffect(MISCREG_HCR), + readMiscRegNoEffect(MISCREG_CPSR), + readMiscRegNoEffect(MISCREG_SCR)); + } case MISCREG_ISR_EL1: - return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( - readMiscRegNoEffect(MISCREG_HCR_EL2), - readMiscRegNoEffect(MISCREG_CPSR), - readMiscRegNoEffect(MISCREG_SCR_EL3)); + { + auto ic = dynamic_cast<ArmISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + return ic->getISR( + readMiscRegNoEffect(MISCREG_HCR_EL2), + readMiscRegNoEffect(MISCREG_CPSR), + readMiscRegNoEffect(MISCREG_SCR_EL3)); + } case MISCREG_DCZID_EL0: return 0x04; // DC ZVA clear 64-byte chunks case MISCREG_HCPTR: diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa index f054bc862..d584d8225 100644 --- a/src/arch/arm/isa/includes.isa +++ b/src/arch/arm/isa/includes.isa @@ -96,6 +96,7 @@ output exec {{ #include <cmath> #include "arch/arm/faults.hh" +#include "arch/arm/interrupts.hh" #include "arch/arm/isa.hh" #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index ecf09aab5..b2dc2f6d8 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -756,8 +756,9 @@ let {{ // WFI doesn't sleep if interrupts are pending (masked or not) ThreadContext *tc = xc->tcBase(); - if (tc->getCpuPtr()->getInterruptController( - tc->threadId())->checkWfiWake(hcr, cpsr, scr)) { + auto *ic = dynamic_cast<ArmISA::Interrupts *>( + tc->getCpuPtr()->getInterruptController(tc->threadId())); + if (ic->checkWfiWake(hcr, cpsr, scr)) { PseudoInst::quiesceSkip(tc); } else { fault = trapWFx(tc, cpsr, scr, false); |