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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-14 15:10:27 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-04-29 08:49:25 +0000 |
commit | ae891622fa5ad2707c9c0551cddf7f0e2d9919b3 (patch) | |
tree | 21a10243ba52832505f44df03b81b9b90e0ad2fd /src/arch/arm | |
parent | 529284becb4610016bdea7a5a40d1be73e2ec697 (diff) | |
download | gem5-ae891622fa5ad2707c9c0551cddf7f0e2d9919b3.tar.xz |
arch-arm: Faults DebugFlag now printing inst opcode if available
This makes it easier to debug unimplemented instructions.
Change-Id: Iaaa288037326722f07251299fd68eacb2e295376
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18396
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/faults.cc | 37 | ||||
-rw-r--r-- | src/arch/arm/faults.hh | 4 |
2 files changed, 29 insertions, 12 deletions
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 9cd068f7f..94374714b 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -496,10 +496,7 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) // if we have a valid instruction then use it to annotate this fault with // extra information. This is used to generate the correct fault syndrome // information - if (inst) { - ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); - armInst->annotateFault(this); - } + ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst); // Ensure Secure state if initially in Monitor mode if (have_security && saved_cpsr.mode == MODE_MON) { @@ -587,8 +584,10 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) } Addr newPc = getVector(tc); - DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", - name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); + DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x " + "%s\n", name(), cpsr, curPc, tc->readIntReg(INTREG_LR), + newPc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) : + std::string()); PCState pc(newPc); pc.thumb(cpsr.t); pc.nextThumb(pc.thumb()); @@ -673,26 +672,40 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) cpsr.ss = 0; tc->setMiscReg(MISCREG_CPSR, cpsr); + // If we have a valid instruction then use it to annotate this fault with + // extra information. This is used to generate the correct fault syndrome + // information + ArmStaticInst *arm_inst M5_VAR_USED = instrAnnotate(inst); + // Set PC to start of exception handler Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL); DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " - "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); + "elr:%#x newVec: %#x %s\n", name(), cpsr, curr_pc, ret_addr, + new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) : + std::string()); PCState pc(new_pc); pc.aarch64(!cpsr.width); pc.nextAArch64(!cpsr.width); pc.illegalExec(false); tc->pcState(pc); - // If we have a valid instruction then use it to annotate this fault with - // extra information. This is used to generate the correct fault syndrome - // information - if (inst) - static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); // Save exception syndrome if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) setSyndrome(tc, getSyndromeReg64()); } +ArmStaticInst * +ArmFault::instrAnnotate(const StaticInstPtr &inst) +{ + if (inst) { + auto arm_inst = static_cast<ArmStaticInst *>(inst.get()); + arm_inst->annotateFault(this); + return arm_inst; + } else { + return nullptr; + } +} + Addr Reset::getVector(ThreadContext *tc) { diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh index 859fd3489..e04a0dcc6 100644 --- a/src/arch/arm/faults.hh +++ b/src/arch/arm/faults.hh @@ -60,6 +60,8 @@ namespace ArmISA { typedef Addr FaultOffset; +class ArmStaticInst; + class ArmFault : public FaultBase { protected: @@ -212,6 +214,8 @@ class ArmFault : public FaultBase void invoke64(ThreadContext *tc, const StaticInstPtr &inst = StaticInst::nullStaticInstPtr); void update(ThreadContext *tc); + + ArmStaticInst *instrAnnotate(const StaticInstPtr &inst); virtual void annotate(AnnotationIDs id, uint64_t val) {} virtual FaultStat& countStat() = 0; virtual FaultOffset offset(ThreadContext *tc) = 0; |