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authorCiro Santilli <ciro.santilli@arm.com>2018-11-15 00:00:00 +0000
committerCiro Santilli <ciro.santilli@arm.com>2018-12-03 10:43:15 +0000
commitb5cc34d767410e98f54f2955bb274f0f8c3708e4 (patch)
tree6d165ae4757c6f844e695180f8ebbe6568166641 /src/arch/arm
parentcb5479e45a9d6c3166fbee6f12bce33a64c98258 (diff)
downloadgem5-b5cc34d767410e98f54f2955bb274f0f8c3708e4.tar.xz
arch-arm: correctly set floats from GDB on aarch64
aarch64 floating point registers are now stored as vector type, but this was not updated in the stub. Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42 Reviewed-on: https://gem5-review.googlesource.com/c/14498 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r--src/arch/arm/remote_gdb.cc25
-rw-r--r--src/arch/arm/remote_gdb.hh2
2 files changed, 16 insertions, 11 deletions
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 38207d494..f3ffa8589 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -203,11 +203,13 @@ RemoteGDB::AArch64GdbRegCache::getRegs(ThreadContext *context)
r.pc = context->pcState().pc();
r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
- for (int i = 0; i < 32*4; i += 4) {
- r.v[i + 0] = context->readFloatRegBits(i + 2);
- r.v[i + 1] = context->readFloatRegBits(i + 3);
- r.v[i + 2] = context->readFloatRegBits(i + 0);
- r.v[i + 3] = context->readFloatRegBits(i + 1);
+ size_t base = 0;
+ for (int i = 0; i < NumVecV8ArchRegs; i++) {
+ auto v = (context->readVecReg(RegId(VecRegClass, i))).as<VecElem>();
+ for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
+ r.v[base] = v[j];
+ base++;
+ }
}
}
@@ -227,11 +229,14 @@ RemoteGDB::AArch64GdbRegCache::setRegs(ThreadContext *context) const
// mapped.
context->setIntReg(INTREG_SPX, r.spx);
- for (int i = 0; i < 32*4; i += 4) {
- context->setFloatRegBits(i + 2, r.v[i + 0]);
- context->setFloatRegBits(i + 3, r.v[i + 1]);
- context->setFloatRegBits(i + 0, r.v[i + 2]);
- context->setFloatRegBits(i + 1, r.v[i + 3]);
+ size_t base = 0;
+ for (int i = 0; i < NumVecV8ArchRegs; i++) {
+ auto v = (context->getWritableVecReg(
+ RegId(VecRegClass, i))).as<VecElem>();
+ for (size_t j = 0; j < NumVecElemPerVecReg; j++) {
+ v[j] = r.v[base];
+ base++;
+ }
}
}
diff --git a/src/arch/arm/remote_gdb.hh b/src/arch/arm/remote_gdb.hh
index e59d7b045..10fcb6d4a 100644
--- a/src/arch/arm/remote_gdb.hh
+++ b/src/arch/arm/remote_gdb.hh
@@ -96,7 +96,7 @@ class RemoteGDB : public BaseRemoteGDB
uint64_t spx;
uint64_t pc;
uint32_t cpsr;
- uint32_t v[32*4];
+ VecElem v[NumVecV8ArchRegs * NumVecElemPerVecReg];
} M5_ATTR_PACKED r;
public:
char *data() const { return (char *)&r; }