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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-12-14 11:16:15 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-25 12:55:27 +0000 |
| commit | d8dd86d4ce94e3e10d9369c0cb4287dd402a9401 (patch) | |
| tree | 8aaf104af8ee4c49f090ad41be8fb687a358b819 /src/arch/arm | |
| parent | 3d15150d715521b8ff9778dbc90061dc9ab72b8e (diff) | |
| download | gem5-d8dd86d4ce94e3e10d9369c0cb4287dd402a9401.tar.xz | |
arch: Fix VecElem Operand generation in ISA parser
Fixes include:
* Change of reg_class: VecElemClass in lieau of non-existing
VectorElemClass.
* Removal of unused regId in operand constructor
* makeRead and makeWrite are using VecElem (which is a typedef
of uint32_t) as a source/destination type, regardless of the real
operand type (which is specified by ctype)
Change-Id: I4588e1120e1fc8fdb68b2b2f05d5e3692c55b2e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15602
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/arm')
0 files changed, 0 insertions, 0 deletions