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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-08-20 10:48:52 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-09-06 11:53:49 +0000 |
| commit | f8ac63a289a4e411e2c1779ef7ee1508de2fd329 (patch) | |
| tree | 8bbf404e8f78357513b9787d171ce9cf330ddc34 /src/arch/arm | |
| parent | 2cac191491bbce22383d4fb81ea694e656b3c294 (diff) | |
| download | gem5-f8ac63a289a4e411e2c1779ef7ee1508de2fd329.tar.xz | |
arch-arm: SGI registers undecoded in AArch32
Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 87cc3fde3..cad123fcc 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -962,6 +962,18 @@ decodeCP15Reg64(unsigned crm, unsigned opc1) return MISCREG_CNTHP_CVAL; } break; + case 12: + switch (opc1) { + case 0: + return MISCREG_ICC_SGI1R; + case 1: + return MISCREG_ICC_ASGI1R; + case 2: + return MISCREG_ICC_SGI0R; + default: + break; + } + break; case 15: if (opc1 == 0) return MISCREG_CPUMERRSR; |