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author | Gabe Black <gabeblack@google.com> | 2019-04-24 17:19:23 -0700 |
---|---|---|
committer | Gabe Black <gabeblack@google.com> | 2019-04-28 03:09:09 +0000 |
commit | fce9c7a26f8c8a29d51c319c876a7bf0a32404a7 (patch) | |
tree | 61cf66e892473fafab9e0e7726750542a0be92b0 /src/arch/arm | |
parent | cdcc55a6a8fe9b4625b316a8d8845366ccfa71c9 (diff) | |
download | gem5-fce9c7a26f8c8a29d51c319c876a7bf0a32404a7.tar.xz |
mem: Remove the ISA specialized versions of port proxy's read/write.
These selected their behavior based on ifdefs and had to be disabled
when on the NULL ISA. The versions which take an explicit endianness
have been renamed to just read/write instead of readGtoH and writeHtoG
since the direction of the translation is obvious from context.
Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm')
-rw-r--r-- | src/arch/arm/semihosting.cc | 30 | ||||
-rw-r--r-- | src/arch/arm/stacktrace.cc | 6 |
2 files changed, 18 insertions, 18 deletions
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc index 51107cbf7..3f9c0955c 100644 --- a/src/arch/arm/semihosting.cc +++ b/src/arch/arm/semihosting.cc @@ -176,7 +176,7 @@ ArmSemihosting::call64(ThreadContext *tc, uint32_t op, uint64_t param) DPRINTF(Semihosting, "Semihosting call64: %s(0x%x)\n", call->name, param); argv[0] = param; for (int i = 0; i < call->argc64; ++i) { - argv[i + 1] = proxy.readGtoH<uint64_t>(param + i * 8, endian); + argv[i + 1] = proxy.read<uint64_t>(param + i * 8, endian); DPRINTF(Semihosting, "\t: 0x%x\n", argv[i + 1]); } @@ -211,7 +211,7 @@ ArmSemihosting::call32(ThreadContext *tc, uint32_t op, uint32_t param) DPRINTF(Semihosting, "Semihosting call32: %s(0x%x)\n", call->name, param); argv[0] = param; for (int i = 0; i < call->argc32; ++i) { - argv[i + 1] = proxy.readGtoH<uint32_t>(param + i * 4, endian); + argv[i + 1] = proxy.read<uint32_t>(param + i * 4, endian); DPRINTF(Semihosting, "\t: 0x%x\n", argv[i + 1]); } @@ -556,9 +556,9 @@ ArmSemihosting::callGetCmdLine(ThreadContext *tc, bool aarch64, (const uint8_t *)cmdLine.c_str(), cmdLine.size() + 1); if (aarch64) - proxy.writeHtoG<uint64_t>(argv[0] + 1 * 8, cmdLine.size(), endian); + proxy.write<uint64_t>(argv[0] + 1 * 8, cmdLine.size(), endian); else - proxy.writeHtoG<uint32_t>(argv[0] + 1 * 4, cmdLine.size(), endian); + proxy.write<uint32_t>(argv[0] + 1 * 4, cmdLine.size(), endian); return retOK(0); } else { return retError(0); @@ -609,15 +609,15 @@ ArmSemihosting::callHeapInfo(ThreadContext *tc, bool aarch64, PortProxy &proxy = physProxy(tc); ByteOrder endian = ArmISA::byteOrder(tc); if (aarch64) { - proxy.writeHtoG<uint64_t>(base + 0 * 8, heap_base, endian); - proxy.writeHtoG<uint64_t>(base + 1 * 8, heap_limit, endian); - proxy.writeHtoG<uint64_t>(base + 2 * 8, stack_base, endian); - proxy.writeHtoG<uint64_t>(base + 3 * 8, stack_limit, endian); + proxy.write<uint64_t>(base + 0 * 8, heap_base, endian); + proxy.write<uint64_t>(base + 1 * 8, heap_limit, endian); + proxy.write<uint64_t>(base + 2 * 8, stack_base, endian); + proxy.write<uint64_t>(base + 3 * 8, stack_limit, endian); } else { - proxy.writeHtoG<uint32_t>(base + 0 * 4, heap_base, endian); - proxy.writeHtoG<uint32_t>(base + 1 * 4, heap_limit, endian); - proxy.writeHtoG<uint32_t>(base + 2 * 4, stack_base, endian); - proxy.writeHtoG<uint32_t>(base + 3 * 4, stack_limit, endian); + proxy.write<uint32_t>(base + 0 * 4, heap_base, endian); + proxy.write<uint32_t>(base + 1 * 4, heap_limit, endian); + proxy.write<uint32_t>(base + 2 * 4, stack_base, endian); + proxy.write<uint32_t>(base + 3 * 4, stack_limit, endian); } return retOK(0); @@ -666,10 +666,10 @@ ArmSemihosting::callElapsed(ThreadContext *tc, bool aarch64, const uint64_t tick = semiTick(curTick()); if (aarch64) { - proxy.writeHtoG<uint64_t>(argv[0], tick, endian); + proxy.write<uint64_t>(argv[0], tick, endian); } else { - proxy.writeHtoG<uint32_t>(argv[0] + 0 * 4, tick, endian); - proxy.writeHtoG<uint32_t>(argv[0] + 1 * 4, tick >> 32, endian); + proxy.write<uint32_t>(argv[0] + 0 * 4, tick, endian); + proxy.write<uint32_t>(argv[0] + 1 * 4, tick >> 32, endian); } return retOK(0); diff --git a/src/arch/arm/stacktrace.cc b/src/arch/arm/stacktrace.cc index de5777554..b4dbf728b 100644 --- a/src/arch/arm/stacktrace.cc +++ b/src/arch/arm/stacktrace.cc @@ -54,7 +54,7 @@ readSymbol(ThreadContext *tc, const std::string name) if (!symtab->findAddress(name, addr)) panic("thread info not compiled into kernel\n"); - return vp.readGtoH<int32_t>(addr); + return vp.read<int32_t>(addr, GuestByteOrder); } ProcessInfo::ProcessInfo(ThreadContext *_tc) : tc(_tc) @@ -76,7 +76,7 @@ ProcessInfo::task(Addr ksp) const Addr tsk; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - tsk = vp.readGtoH<Addr>(base + task_off); + tsk = vp.read<Addr>(base + task_off, GuestByteOrder); return tsk; } @@ -91,7 +91,7 @@ ProcessInfo::pid(Addr ksp) const uint16_t pd; FSTranslatingPortProxy &vp = tc->getVirtProxy(); - pd = vp.readGtoH<uint16_t>(task + pid_off); + pd = vp.read<uint16_t>(task + pid_off, GuestByteOrder); return pd; } |