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authorGabe Black <gabeblack@google.com>2018-10-12 05:03:38 -0700
committerGabe Black <gabeblack@google.com>2018-10-12 23:58:58 +0000
commita22030133d9bed4e4e93f549b7993705421be845 (patch)
tree5fac4e73fd4a35d6175949ed1f172e05165d2412 /src/arch/generic/mmapped_ipr.cc
parent657b3ce63f28fe85aedf3a71e7c459a114c0de16 (diff)
downloadgem5-a22030133d9bed4e4e93f549b7993705421be845.tar.xz
arch: Explicitly specify the endianness in the generic mem helpers.
This avoids using the accessors which automatically assume an endianness, requiring the memory system to know what the guest ISA is. Change-Id: I863fa4116f00e77b801a2f8ea2fbe34e7f55fd5f Reviewed-on: https://gem5-review.googlesource.com/c/13461 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/generic/mmapped_ipr.cc')
-rw-r--r--src/arch/generic/mmapped_ipr.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/generic/mmapped_ipr.cc b/src/arch/generic/mmapped_ipr.cc
index c908eff01..14e2bafbd 100644
--- a/src/arch/generic/mmapped_ipr.cc
+++ b/src/arch/generic/mmapped_ipr.cc
@@ -47,7 +47,7 @@ handlePseudoInst(ThreadContext *xc, Packet *pkt)
assert((offset >> 16) == 0);
ret = PseudoInst::pseudoInst(xc, func, subfunc);
if (pkt->isRead())
- pkt->set(ret);
+ pkt->set(ret, TheISA::GuestByteOrder);
}
Cycles