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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
| tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/arch/generic/tlb.hh | |
| parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
| download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz | |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/arch/generic/tlb.hh')
| -rw-r--r-- | src/arch/generic/tlb.hh | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index e0becf727..89180341c 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -77,7 +77,7 @@ class BaseTLB : public SimObject * be responsible for cleaning itself up which will happen in this * function. Once it's called, the object is no longer valid. */ - virtual void finish(const Fault &fault, RequestPtr req, + virtual void finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; /** This function is used by the page table walker to determine if it @@ -92,12 +92,12 @@ class BaseTLB : public SimObject virtual void demapPage(Addr vaddr, uint64_t asn) = 0; virtual Fault translateAtomic( - RequestPtr req, ThreadContext *tc, Mode mode) = 0; + const RequestPtr &req, ThreadContext *tc, Mode mode) = 0; virtual void translateTiming( - RequestPtr req, ThreadContext *tc, + const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) = 0; virtual Fault - translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) + translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) { panic("Not implemented.\n"); } @@ -117,7 +117,7 @@ class BaseTLB : public SimObject * @return A fault on failure, NoFault otherwise. */ virtual Fault finalizePhysical( - RequestPtr req, ThreadContext *tc, Mode mode) const = 0; + const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0; /** * Remove all entries from the TLB @@ -154,13 +154,13 @@ class GenericTLB : public BaseTLB void demapPage(Addr vaddr, uint64_t asn) override; Fault translateAtomic( - RequestPtr req, ThreadContext *tc, Mode mode) override; + const RequestPtr &req, ThreadContext *tc, Mode mode) override; void translateTiming( - RequestPtr req, ThreadContext *tc, + const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) override; Fault finalizePhysical( - RequestPtr req, ThreadContext *tc, Mode mode) const override; + const RequestPtr &req, ThreadContext *tc, Mode mode) const override; }; #endif // __ARCH_GENERIC_TLB_HH__ |