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| author | Gabe Black <gabeblack@google.com> | 2019-08-17 00:13:09 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-08-28 02:14:21 +0000 |
| commit | c387a212d98024e42e4267ff364c2976f976d666 (patch) | |
| tree | de4f67564682bb2d8633dc99f6cb048481c7e370 /src/arch/generic | |
| parent | 4d503eeffee054de0aab10962c345ca4bcb54140 (diff) | |
| download | gem5-c387a212d98024e42e4267ff364c2976f976d666.tar.xz | |
mem: Eliminate the Base(Slave|Master)Port classes.
The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.
Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/generic')
| -rw-r--r-- | src/arch/generic/tlb.hh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh index cd33ef4c9..8aab5135a 100644 --- a/src/arch/generic/tlb.hh +++ b/src/arch/generic/tlb.hh @@ -48,7 +48,6 @@ #include "sim/sim_object.hh" class ThreadContext; -class BaseMasterPort; class BaseTLB : public SimObject { |