diff options
author | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-10-15 13:24:35 +0200 |
---|---|---|
committer | Andreas Sandberg <andreas@sandberg.pp.se> | 2013-10-15 13:24:35 +0200 |
commit | 5e7738467bbc928ff163afc5b94c81385cc6778e (patch) | |
tree | ae407db632d031b2d1144347d80cb16073219081 /src/arch/generic | |
parent | c753b273dc1d18114035c4bd5c61bd59fa9f9cfe (diff) | |
download | gem5-5e7738467bbc928ff163afc5b94c81385cc6778e.tar.xz |
mem: Use a flag instead of address bit 63 for generic IPRs
Using address bit 63 to identify generic IPRs caused problems on
SPARC, where IPRs are heavily used. This changeset redefines how
generic IPRs are identified. Instead of using bit 63, we now use a
separate flag (GENERIC_IPR) a memory request.
Diffstat (limited to 'src/arch/generic')
-rw-r--r-- | src/arch/generic/mmapped_ipr.cc | 4 | ||||
-rw-r--r-- | src/arch/generic/mmapped_ipr.hh | 21 |
2 files changed, 8 insertions, 17 deletions
diff --git a/src/arch/generic/mmapped_ipr.cc b/src/arch/generic/mmapped_ipr.cc index 3d85eea9f..1a356a5d5 100644 --- a/src/arch/generic/mmapped_ipr.cc +++ b/src/arch/generic/mmapped_ipr.cc @@ -53,7 +53,7 @@ Cycles GenericISA::handleGenericIprRead(ThreadContext *xc, Packet *pkt) { Addr va(pkt->getAddr()); - Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT); + Addr cls(va >> IPR_CLASS_SHIFT); switch (cls) { case IPR_CLASS_PSEUDO_INST: @@ -70,7 +70,7 @@ Cycles GenericISA::handleGenericIprWrite(ThreadContext *xc, Packet *pkt) { Addr va(pkt->getAddr()); - Addr cls((va & IPR_CLASS_MASK) >> IPR_CLASS_SHIFT); + Addr cls(va >> IPR_CLASS_SHIFT); switch (cls) { case IPR_CLASS_PSEUDO_INST: diff --git a/src/arch/generic/mmapped_ipr.hh b/src/arch/generic/mmapped_ipr.hh index 55ce6e4d5..a371699eb 100644 --- a/src/arch/generic/mmapped_ipr.hh +++ b/src/arch/generic/mmapped_ipr.hh @@ -49,23 +49,12 @@ namespace GenericISA * Memory requests with the MMAPPED_IPR flag are generally mapped * to registers. There is a class of these registers that are * internal to gem5, for example gem5 pseudo-ops in virtualized - * mode. - * - * In order to make the IPR space manageable we always set bit 63 - * (IPR_GENERIC) for accesses that should be handled by the - * generic ISA code. Architectures may use the rest of the IPR - * space internally. + * mode. Such IPRs always have the flag GENERIC_IPR set and are + * handled by this code. */ - /** Is this a generic IPR access? */ - const Addr IPR_GENERIC = ULL(0x8000000000000000); - - /** @{ */ - /** Mask when extracting the class of a generic IPR */ - const Addr IPR_CLASS_MASK = ULL(0x7FFF000000000000); /** Shift amount when extracting the class of a generic IPR */ const int IPR_CLASS_SHIFT = 48; - /** @} */ /** Mask to extract the offset in within a generic IPR class */ const Addr IPR_IN_CLASS_MASK = ULL(0x0000FFFFFFFFFFFF); @@ -94,7 +83,7 @@ namespace GenericISA inline Addr iprAddressPseudoInst(uint8_t func, uint8_t subfunc) { - return IPR_GENERIC | (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) | + return (IPR_CLASS_PSEUDO_INST << IPR_CLASS_SHIFT) | (func << 8) | subfunc; } @@ -113,7 +102,9 @@ namespace GenericISA inline bool isGenericIprAccess(const Packet *pkt) { - return pkt->getAddr() & IPR_GENERIC; + Request::Flags flags(pkt->req->getFlags()); + return (flags & Request::MMAPPED_IPR) && + (flags & Request::GENERIC_IPR); } /** |