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authorNathanael Premillieu <nathanael.premillieu@arm.com>2017-04-05 12:46:06 -0500
committerAndreas Sandberg <andreas.sandberg@arm.com>2017-07-05 14:43:49 +0000
commit5e8287d2e2eaf058495442ea9e32fafc343a0b53 (patch)
tree7d0891b8984926f8e404d6ca8247f45695f9fc9b /src/arch/generic
parent864f87f9c56a66dceeca0f4e9470fbaa3001b627 (diff)
downloadgem5-5e8287d2e2eaf058495442ea9e32fafc343a0b53.tar.xz
arch, cpu: Architectural Register structural indexing
Replace the unified register mapping with a structure associating a class and an index. It is now much easier to know which class of register the index is referring to. Also, when adding a new class there is no need to modify existing ones. Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2700
Diffstat (limited to 'src/arch/generic')
-rw-r--r--src/arch/generic/types.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 78ead6832..bb6eafd66 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -37,6 +37,9 @@
#include "base/types.hh"
#include "sim/serialize.hh"
+// Logical register index type.
+typedef uint16_t RegIndex;
+
namespace GenericISA
{