cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705

4 files changed, 129 insertions, 0 deletions

diff --git a/src/arch/generic/ISACommon.py b/src/arch/generic/ISACommon.py
new file mode 100644
index 000000000..7777dc27e
--- /dev/null
+++ b/src/arch/generic/ISACommon.py
@@ -0,0 +1,50 @@
+# Copyright (c) 2016 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Rekai Gonzalez
+
+from m5.params import *
+from m5.proxy import *
+from m5.SimObject import SimObject
+
+class VecRegRenameMode(Enum):
+    '''Enum for Rename Mode in rename map
+        Elem: Each native-elem in a vector register is renamed independently.
+        Full: Vectors are renamed as one unit.'''
+
+    vals = ['Full', 'Elem']
+
+
+__all__ = ['VecRegRenameMode']
diff --git a/src/arch/generic/SConscript b/src/arch/generic/SConscript
index c87ad671f..7123eaf4a 100644
--- a/src/arch/generic/SConscript
+++ b/src/arch/generic/SConscript
@@ -1,3 +1,15 @@
+# Copyright (c) 2016 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2012 Google
 # All rights reserved.
 #
@@ -36,6 +48,7 @@ Source('mmapped_ipr.cc')
 Source('tlb.cc')
 
 SimObject('BaseTLB.py')
+SimObject('ISACommon.py')
 
 DebugFlag('TLB')
 Source('pseudo_inst.cc')
diff --git a/src/arch/generic/traits.hh b/src/arch/generic/traits.hh
new file mode 100644
index 000000000..3dc6b30ee
--- /dev/null
+++ b/src/arch/generic/traits.hh
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Rekai Gonzalez
+ */
+
+/* Auxiliary structs for architecture traits. */
+
+#ifndef __ARCH_COMMON_TRAITS_HH__
+#define __ARCH_COMMON_TRAITS_HH__
+
+#include "enums/VecRegRenameMode.hh"
+
+/** Helper structure to get the vector register mode for a given ISA.
+ * This way we implement a default 'full' mode, and only those ISA that care
+ * have to actually specialise the template to forward the call to the
+ * appropriate member of the ISA.
+ */
+template <typename ISA>
+struct initRenameMode
+{
+    static Enums::VecRegRenameMode mode(const ISA*) { return Enums::Full; }
+    /**
+     * Compare the initial rename mode of two instances of the ISA.
+     * Result is true by definition, as the default mode is Full.
+     * */
+    static bool equals(const ISA*, const ISA*) { return true; }
+};
+
+#endif /* __ARCH_COMMON_TRAITS_HH__ */
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index bb6eafd66..353112913 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -40,6 +40,9 @@
 // Logical register index type.
 typedef uint16_t RegIndex;
 
+/** Logical vector register elem index type. */
+using ElemIndex = uint16_t;
+
 namespace GenericISA
 {