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authorGabe Black <gabeblack@google.com>2019-10-29 19:31:37 -0700
committerGabe Black <gabeblack@google.com>2019-11-18 20:02:31 +0000
commit697e55995626f24658ce443287cd1ba90c2f68eb (patch)
tree4f19d13ded04c4d4b3ae53607fa90638ba96a7bd /src/arch/generic
parent17a0c0b00644c37e9d8539a9de0a02dc213a6834 (diff)
downloadgem5-697e55995626f24658ce443287cd1ba90c2f68eb.tar.xz
arch: Make and use endian specific versions of the mem helpers.
Rather than using TheISA to pick an endian conversion function, we can have a version defined for big and little endian and call the right one from the ISA code. Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/generic')
-rw-r--r--src/arch/generic/memhelpers.hh109
1 files changed, 97 insertions, 12 deletions
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index fa1af2694..62866bf0c 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -62,17 +62,31 @@ initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
}
/// Extract the data returned from a timing mode read.
-template <class MemT>
+template <ByteOrder Order, class MemT>
void
getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
{
- mem = pkt->get<MemT>(TheISA::GuestByteOrder);
+ mem = pkt->get<MemT>(Order);
if (traceData)
traceData->setData(mem);
}
+template <class MemT>
+void
+getMemLE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+{
+ getMem<LittleEndianByteOrder>(pkt, mem, traceData);
+}
+
+template <class MemT>
+void
+getMemBE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+{
+ getMem<BigEndianByteOrder>(pkt, mem, traceData);
+}
+
/// Read from memory in atomic mode.
-template <class XC, class MemT>
+template <ByteOrder Order, class XC, class MemT>
Fault
readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
@@ -80,50 +94,103 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
memset(&mem, 0, sizeof(mem));
Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags);
if (fault == NoFault) {
- mem = TheISA::gtoh(mem);
+ mem = gtoh(mem, Order);
if (traceData)
traceData->setData(mem);
}
return fault;
}
-/// Write to memory in timing mode.
template <class XC, class MemT>
Fault
+readMemAtomicLE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+ Request::Flags flags)
+{
+ return readMemAtomic<LittleEndianByteOrder>(
+ xc, traceData, addr, mem, flags);
+}
+
+template <class XC, class MemT>
+Fault
+readMemAtomicBE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+ Request::Flags flags)
+{
+ return readMemAtomic<BigEndianByteOrder>(xc, traceData, addr, mem, flags);
+}
+
+/// Write to memory in timing mode.
+template <ByteOrder Order, class XC, class MemT>
+Fault
writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
}
- mem = TheISA::htog(mem);
+ mem = htog(mem, Order);
return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res);
}
-/// Write to memory in atomic mode.
template <class XC, class MemT>
Fault
+writeMemTimingLE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+ Request::Flags flags, uint64_t *res)
+{
+ return writeMemTiming<LittleEndianByteOrder>(
+ xc, traceData, mem, addr, flags, res);
+}
+
+template <class XC, class MemT>
+Fault
+writeMemTimingBE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+ Request::Flags flags, uint64_t *res)
+{
+ return writeMemTiming<BigEndianByteOrder>(
+ xc, traceData, mem, addr, flags, res);
+}
+
+/// Write to memory in atomic mode.
+template <ByteOrder Order, class XC, class MemT>
+Fault
writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
if (traceData) {
traceData->setData(mem);
}
- MemT host_mem = TheISA::htog(mem);
+ MemT host_mem = htog(mem, Order);
Fault fault =
xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res);
if (fault == NoFault && res != NULL) {
if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND)
- *(MemT *)res = TheISA::gtoh(*(MemT *)res);
+ *(MemT *)res = gtoh(*(MemT *)res, Order);
else
- *res = TheISA::gtoh(*res);
+ *res = gtoh(*res, Order);
}
return fault;
}
-/// Do atomic read-modify-write (AMO) in atomic mode
template <class XC, class MemT>
Fault
+writeMemAtomicLE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+ Addr addr, Request::Flags flags, uint64_t *res)
+{
+ return writeMemAtomic<LittleEndianByteOrder>(
+ xc, traceData, mem, addr, flags, res);
+}
+
+template <class XC, class MemT>
+Fault
+writeMemAtomicBE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+ Addr addr, Request::Flags flags, uint64_t *res)
+{
+ return writeMemAtomic<BigEndianByteOrder>(
+ xc, traceData, mem, addr, flags, res);
+}
+
+/// Do atomic read-modify-write (AMO) in atomic mode
+template <ByteOrder Order, class XC, class MemT>
+Fault
amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
@@ -137,13 +204,31 @@ amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
std::move(amo_op));
if (fault == NoFault) {
- mem = TheISA::gtoh(mem);
+ mem = gtoh(mem, Order);
if (traceData)
traceData->setData(mem);
}
return fault;
}
+template <class XC, class MemT>
+Fault
+amoMemAtomicLE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
+ Request::Flags flags, AtomicOpFunctor *_amo_op)
+{
+ return amoMemAtomic<LittleEndianByteOrder>(
+ xc, traceData, mem, addr, flags, _amo_op);
+}
+
+template <class XC, class MemT>
+Fault
+amoMemAtomicBE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
+ Request::Flags flags, AtomicOpFunctor *_amo_op)
+{
+ return amoMemAtomic<BigEndianByteOrder>(
+ xc, traceData, mem, addr, flags, _amo_op);
+}
+
/// Do atomic read-modify-wrote (AMO) in timing mode
template <class XC, class MemT>
Fault