arch-arm,cpu: Add initial support for Arm SVE

This changeset adds initial support for the Arm Scalable Vector Extension
(SVE) by implementing:
- support for most data-processing instructions (no loads/stores yet);
- basic system-level support.

Additional authors:
- Javier Setoain <javier.setoain@arm.com>
- Gabor Dozsa <gabor.dozsa@arm.com>
- Giacomo Travaglini <giacomo.travaglini@arm.com>

Thanks to Pau Cabre for his contribution of bugfixes.

Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/src/arch/generic/vec_reg.hh b/src/arch/generic/vec_reg.hh
index f26a8c8ad..ed2545c64 100644
--- a/src/arch/generic/vec_reg.hh
+++ b/src/arch/generic/vec_reg.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2016, 2018 ARM Limited
+ * Copyright (c) 2015-2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -154,6 +154,8 @@
 #include "base/cprintf.hh"
 #include "base/logging.hh"
 
+constexpr unsigned MaxVecRegLenInBytes = 256;
+
 template <size_t Sz>
 class VecRegContainer;
 
@@ -271,6 +273,8 @@ class VecRegContainer
 {
   static_assert(Sz > 0,
           "Cannot create Vector Register Container of zero size");
+  static_assert(Sz <= MaxVecRegLenInBytes,
+          "Vector Register size limit exceeded");
   public:
     static constexpr size_t SIZE = Sz;
     using Container = std::array<uint8_t,Sz>;
@@ -519,6 +523,7 @@ class VecLaneT
     friend class VecRegContainer<32>;
     friend class VecRegContainer<64>;
     friend class VecRegContainer<128>;
+    friend class VecRegContainer<MaxVecRegLenInBytes>;
 
     /** My type alias. */
     using MyClass = VecLaneT<VecElem, Const>;