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authorTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:43 -0400
committerTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:43 -0400
commit844fb845a51b15f13c7c744e0d5fdf5567c3da98 (patch)
tree407cd19c909cdf3cd4da7947ad86dfbd4470ef68 /src/arch/hsail/gpu_types.hh
parentd327cdba078e0956596513b518731e9ec730723f (diff)
downloadgem5-844fb845a51b15f13c7c744e0d5fdf5567c3da98.tar.xz
gpu-compute, hsail: make the PC a byte address, not an instruction index
currently the PC is incremented on an instruction granularity, and not as an instruction's byte address. machine ISA instructions assume the PC is a byte address, and is incremented accordingly. here we make the GPU model, and the HSAIL instructions treat the PC as a byte address as well.
Diffstat (limited to 'src/arch/hsail/gpu_types.hh')
-rw-r--r--src/arch/hsail/gpu_types.hh2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/hsail/gpu_types.hh b/src/arch/hsail/gpu_types.hh
index 4b3a66a9a..7b6689d67 100644
--- a/src/arch/hsail/gpu_types.hh
+++ b/src/arch/hsail/gpu_types.hh
@@ -51,7 +51,7 @@ namespace HsailISA
// our model uses to represent an actual instruction. In
// the case of HSAIL this is just an index into a list of
// instruction objects.
- typedef uint64_t RawMachInst;
+ typedef uint32_t RawMachInst;
// The MachInst is a representation of an instruction
// that has more information than just the machine code.