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authorBrandon Potter <brandon.potter@amd.com>2016-12-02 18:01:57 -0500
committerBrandon Potter <brandon.potter@amd.com>2016-12-02 18:01:57 -0500
commit900fd15622f905d53e233ec17e11bc5a1aaf680e (patch)
tree67ca77169281e7699abf2f6689924d184ad0da5e /src/arch/hsail/insts/decl.hh
parent86b375f2f3c5d039a74be6481f11426fb51a5e38 (diff)
downloadgem5-900fd15622f905d53e233ec17e11bc5a1aaf680e.tar.xz
hsail: add stub type and stub out several instructions
Diffstat (limited to 'src/arch/hsail/insts/decl.hh')
-rw-r--r--src/arch/hsail/insts/decl.hh52
1 files changed, 42 insertions, 10 deletions
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index 919a4d9d4..f84cb61e9 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -745,6 +745,38 @@ namespace HsailISA
}
};
+ class Stub : public HsailGPUStaticInst
+ {
+ public:
+ Stub(const Brig::BrigInstBase *ib, const BrigObject *obj,
+ const char *_opcode)
+ : HsailGPUStaticInst(obj, _opcode)
+ {
+ }
+
+ void generateDisassembly() override
+ {
+ disassembly = csprintf("%s", opcode);
+ }
+
+ bool isVectorRegister(int operandIndex) override { return false; }
+ bool isCondRegister(int operandIndex) override { return false; }
+ bool isScalarRegister(int operandIndex) override { return false; }
+ bool isSrcOperand(int operandIndex) override { return false; }
+ bool isDstOperand(int operandIndex) override { return false; }
+ int getOperandSize(int operandIndex) override { return 0; }
+
+ int
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+ {
+ return -1;
+ }
+
+ int numSrcRegOperands() override { return 0; }
+ int numDstRegOperands() override { return 0; }
+ int getNumOperands() override { return 0; }
+ };
+
class SpecialInstNoSrcNoDest : public HsailGPUStaticInst
{
public:
@@ -754,22 +786,22 @@ namespace HsailISA
{
}
- bool isVectorRegister(int operandIndex) { return false; }
- bool isCondRegister(int operandIndex) { return false; }
- bool isScalarRegister(int operandIndex) { return false; }
- bool isSrcOperand(int operandIndex) { return false; }
- bool isDstOperand(int operandIndex) { return false; }
- int getOperandSize(int operandIndex) { return 0; }
+ bool isVectorRegister(int operandIndex) override { return false; }
+ bool isCondRegister(int operandIndex) override { return false; }
+ bool isScalarRegister(int operandIndex) override { return false; }
+ bool isSrcOperand(int operandIndex) override { return false; }
+ bool isDstOperand(int operandIndex) override { return false; }
+ int getOperandSize(int operandIndex) override { return 0; }
int
- getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+ getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
{
return -1;
}
- int numSrcRegOperands() { return 0; }
- int numDstRegOperands() { return 0; }
- int getNumOperands() { return 0; }
+ int numSrcRegOperands() override { return 0; }
+ int numDstRegOperands() override { return 0; }
+ int getNumOperands() override { return 0; }
};
template<typename DestOperandType>