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author | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-10-26 22:47:11 -0400 |
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committer | Tony Gutierrez <anthony.gutierrez@amd.com> | 2016-10-26 22:47:11 -0400 |
commit | 7ac38849abaf6aeccf39137bc8acb9e44d192e82 (patch) | |
tree | 7658e9d741604b310f871756cf051558b30e115e /src/arch/hsail/insts/mem.cc | |
parent | e1ad8035a379cea98ecef92e78d2894f60b2eedd (diff) | |
download | gem5-7ac38849abaf6aeccf39137bc8acb9e44d192e82.tar.xz |
gpu-compute: remove inst enums and use bit flag for attributes
this patch removes the GPUStaticInst enums that were defined in GPU.py.
instead, a simple set of attribute flags that can be set in the base
instruction class are used. this will help unify the attributes of HSAIL
and machine ISA instructions within the model itself.
because the static instrution now carries the attributes, a GPUDynInst
must carry a pointer to a valid GPUStaticInst so a new static kernel launch
instruction is added, which carries the attributes needed to perform a
the kernel launch.
Diffstat (limited to 'src/arch/hsail/insts/mem.cc')
-rw-r--r-- | src/arch/hsail/insts/mem.cc | 63 |
1 files changed, 0 insertions, 63 deletions
diff --git a/src/arch/hsail/insts/mem.cc b/src/arch/hsail/insts/mem.cc index 97d4c902b..6a6928838 100644 --- a/src/arch/hsail/insts/mem.cc +++ b/src/arch/hsail/insts/mem.cc @@ -36,7 +36,6 @@ #include "arch/hsail/insts/mem.hh" #include "arch/hsail/Brig.h" -#include "enums/OpType.hh" using namespace Brig; @@ -44,68 +43,6 @@ namespace HsailISA { const char* atomicOpToString(BrigAtomicOperation brigOp); - Enums::MemOpType - brigAtomicToMemOpType(BrigOpcode brigOpCode, BrigAtomicOperation brigOp) - { - if (brigOpCode == Brig::BRIG_OPCODE_ATOMIC) { - switch (brigOp) { - case BRIG_ATOMIC_AND: - return Enums::MO_AAND; - case BRIG_ATOMIC_OR: - return Enums::MO_AOR; - case BRIG_ATOMIC_XOR: - return Enums::MO_AXOR; - case BRIG_ATOMIC_CAS: - return Enums::MO_ACAS; - case BRIG_ATOMIC_EXCH: - return Enums::MO_AEXCH; - case BRIG_ATOMIC_ADD: - return Enums::MO_AADD; - case BRIG_ATOMIC_WRAPINC: - return Enums::MO_AINC; - case BRIG_ATOMIC_WRAPDEC: - return Enums::MO_ADEC; - case BRIG_ATOMIC_MIN: - return Enums::MO_AMIN; - case BRIG_ATOMIC_MAX: - return Enums::MO_AMAX; - case BRIG_ATOMIC_SUB: - return Enums::MO_ASUB; - default: - fatal("Bad BrigAtomicOperation code %d\n", brigOp); - } - } else if (brigOpCode == Brig::BRIG_OPCODE_ATOMICNORET) { - switch (brigOp) { - case BRIG_ATOMIC_AND: - return Enums::MO_ANRAND; - case BRIG_ATOMIC_OR: - return Enums::MO_ANROR; - case BRIG_ATOMIC_XOR: - return Enums::MO_ANRXOR; - case BRIG_ATOMIC_CAS: - return Enums::MO_ANRCAS; - case BRIG_ATOMIC_EXCH: - return Enums::MO_ANREXCH; - case BRIG_ATOMIC_ADD: - return Enums::MO_ANRADD; - case BRIG_ATOMIC_WRAPINC: - return Enums::MO_ANRINC; - case BRIG_ATOMIC_WRAPDEC: - return Enums::MO_ANRDEC; - case BRIG_ATOMIC_MIN: - return Enums::MO_ANRMIN; - case BRIG_ATOMIC_MAX: - return Enums::MO_ANRMAX; - case BRIG_ATOMIC_SUB: - return Enums::MO_ANRSUB; - default: - fatal("Bad BrigAtomicOperation code %d\n", brigOp); - } - } else { - fatal("Bad BrigAtomicOpcode %d\n", brigOpCode); - } - } - const char* atomicOpToString(BrigAtomicOperation brigOp) { |