gpu-compute, hsail: pass GPUDynInstPtr to getRegisterIndex()

for HSAIL an operand's indices into the register files may be calculated
trivially, because the operands are always read from a register file, or are
an immediate.

for machine ISA, however, an op selector may specify special registers, or
may specify special SGPRs with an alias op selector value. the location of
some of the special registers values are dependent on the size of the RF
in some cases. here we add a way for the underlying getRegisterIndex()
method to know about the size of the RFs, so that it may find the relative
positions of the special register values.

3 files changed, 56 insertions, 18 deletions

diff --git a/src/arch/hsail/insts/branch.hh b/src/arch/hsail/insts/branch.hh
index 6df6f766a..79603f408 100644
--- a/src/arch/hsail/insts/branch.hh
+++ b/src/arch/hsail/insts/branch.hh
@@ -95,7 +95,9 @@ namespace HsailISA
             return target.opSize();
         }
 
-        int getRegisterIndex(int operandIndex) override {
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+        {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.regIndex();
         }
@@ -223,7 +225,9 @@ namespace HsailISA
             else
                 return 1;
         }
-        int getRegisterIndex(int operandIndex) override {
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+        {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             if (!operandIndex)
                 return target.regIndex();
@@ -370,7 +374,9 @@ namespace HsailISA
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.opSize();
         }
-        int getRegisterIndex(int operandIndex) override {
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
+        {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return target.regIndex();
         }
diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh
index 94f23ac1f..c40411ace 100644
--- a/src/arch/hsail/insts/decl.hh
+++ b/src/arch/hsail/insts/decl.hh
@@ -178,7 +178,9 @@ namespace HsailISA
             else
                 return dest.opSize();
         }
-        int getRegisterIndex(int operandIndex) {
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
 
             if (operandIndex < NumSrcOperands)
@@ -313,7 +315,10 @@ namespace HsailISA
             else
                 return dest.opSize();
         }
-        int getRegisterIndex(int operandIndex) {
+
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (!operandIndex)
                 return src0.regIndex();
@@ -477,7 +482,10 @@ namespace HsailISA
             else
                 return dest.opSize();
         }
-        int getRegisterIndex(int operandIndex) {
+
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (!operandIndex)
                 return src0.regIndex();
@@ -643,7 +651,7 @@ namespace HsailISA
             return -1;
 
         //handle positive and negative numbers
-        T tmp = (src0 < 0) ? (~src0) : (src0);
+        T tmp = ((int64_t)src0 < 0) ? (~src0) : (src0);
 
         //the starting pos is MSB
         int pos = 8 * sizeof(T) - 1;
@@ -732,7 +740,12 @@ namespace HsailISA
         bool isSrcOperand(int operandIndex) { return false; }
         bool isDstOperand(int operandIndex) { return false; }
         int getOperandSize(int operandIndex) { return 0; }
-        int getRegisterIndex(int operandIndex) { return -1; }
+
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
+            return -1;
+        }
 
         int numSrcRegOperands() { return 0; }
         int numDstRegOperands() { return 0; }
@@ -777,10 +790,14 @@ namespace HsailISA
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return dest.opSize();
         }
-        int getRegisterIndex(int operandIndex) {
+
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return dest.regIndex();
         }
+
         int numSrcRegOperands() { return 0; }
         int numDstRegOperands() { return dest.isVectorRegister(); }
         int getNumOperands() { return 1; }
@@ -848,10 +865,14 @@ namespace HsailISA
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return dest.opSize();
         }
-        int getRegisterIndex(int operandIndex) {
+
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return dest.regIndex();
         }
+
         int numSrcRegOperands() { return 0; }
         int numDstRegOperands() { return dest.isVectorRegister(); }
         int getNumOperands() { return 1; }
@@ -1171,8 +1192,13 @@ namespace HsailISA
         bool isScalarRegister(int operandIndex) { return false; }
         bool isSrcOperand(int operandIndex) { return false; }
         bool isDstOperand(int operandIndex) { return false; }
-        int  getOperandSize(int operandIndex) { return 0; }
-        int  getRegisterIndex(int operandIndex) { return -1; }
+        int getOperandSize(int operandIndex) { return 0; }
+
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
+        {
+            return -1;
+        }
 
         void
         execute(GPUDynInstPtr gpuDynInst)
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh
index 2e7dfcd1c..36a6cbc79 100644
--- a/src/arch/hsail/insts/mem.hh
+++ b/src/arch/hsail/insts/mem.hh
@@ -146,7 +146,8 @@ namespace HsailISA
             return((operandIndex == 0) ? dest.opSize() :
                    this->addr.opSize());
         }
-        int getRegisterIndex(int operandIndex) override
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.regIndex() :
@@ -377,7 +378,8 @@ namespace HsailISA
             return((operandIndex == 0) ? dest.opSize() :
                    this->addr.opSize());
         }
-        int getRegisterIndex(int operandIndex) override
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             return((operandIndex == 0) ? dest.regIndex() :
@@ -670,7 +672,8 @@ namespace HsailISA
                        AddrOperandType>::dest.opSize());
             return 0;
         }
-        int getRegisterIndex(int operandIndex) override
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if ((num_dest_operands != getNumOperands()) &&
@@ -934,7 +937,8 @@ namespace HsailISA
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.opSize() : this->addr.opSize();
         }
-        int getRegisterIndex(int operandIndex) override
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
         {
             assert(operandIndex >= 0 && operandIndex < getNumOperands());
             return !operandIndex ? src.regIndex() : this->addr.regIndex();
@@ -1144,7 +1148,8 @@ namespace HsailISA
                        AddrOperandType>::src.opSize();
             return 0;
         }
-        int getRegisterIndex(int operandIndex) override
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst) override
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex == num_src_operands)
@@ -1433,7 +1438,8 @@ namespace HsailISA
             else
                 return(dest.opSize());
         }
-        int getRegisterIndex(int operandIndex)
+        int
+        getRegisterIndex(int operandIndex, GPUDynInstPtr gpuDynInst)
         {
             assert((operandIndex >= 0) && (operandIndex < getNumOperands()));
             if (operandIndex < NumSrcOperands)