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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2016-04-07 09:30:20 -0500 |
| commit | c75ff71139d6358678835cca63e35d1135eaf466 (patch) | |
| tree | 0811177db4dca4a237b8e5d7dd65f8ec155cb14e /src/arch/hsail/insts | |
| parent | d99deff8ea296fd28b48da08aba577a1e7dfc01b (diff) | |
| download | gem5-c75ff71139d6358678835cca63e35d1135eaf466.tar.xz | |
mem: Remove threadId from memory request class
In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.
This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
Diffstat (limited to 'src/arch/hsail/insts')
| -rw-r--r-- | src/arch/hsail/insts/mem.hh | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh index 29091f9d1..f2792cd49 100644 --- a/src/arch/hsail/insts/mem.hh +++ b/src/arch/hsail/insts/mem.hh @@ -479,7 +479,7 @@ namespace HsailISA } else { Request *req = new Request(0, vaddr, sizeof(c0), 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, i); + 0, gpuDynInst->wfDynId); gpuDynInst->setRequestFlags(req); PacketPtr pkt = new Packet(req, MemCmd::ReadReq); @@ -528,7 +528,7 @@ namespace HsailISA // create request Request *req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, -1); + 0, gpuDynInst->wfDynId); req->setFlags(Request::ACQUIRE); gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req); } @@ -974,7 +974,7 @@ namespace HsailISA // create request Request *req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, -1); + 0, gpuDynInst->wfDynId); req->setFlags(Request::RELEASE); gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req); @@ -1026,7 +1026,7 @@ namespace HsailISA Request *req = new Request(0, vaddr, sizeof(c0), 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, i); + 0, gpuDynInst->wfDynId); gpuDynInst->setRequestFlags(req); PacketPtr pkt = new Packet(req, MemCmd::WriteReq); @@ -1366,7 +1366,7 @@ namespace HsailISA // create request Request *req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, -1); + 0, gpuDynInst->wfDynId); req->setFlags(Request::RELEASE); gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req); @@ -1477,7 +1477,7 @@ namespace HsailISA Request *req = new Request(0, vaddr, sizeof(c0), 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, i, + 0, gpuDynInst->wfDynId, gpuDynInst->makeAtomicOpFunctor<c0>(e, f, this->opType)); @@ -1533,7 +1533,7 @@ namespace HsailISA // create request Request *req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId, -1); + 0, gpuDynInst->wfDynId); req->setFlags(Request::ACQUIRE); gpuDynInst->computeUnit()->injectGlobalMemFence(gpuDynInst, false, req); } |