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author | Brandon Potter <brandon.potter@amd.com> | 2016-12-02 18:01:55 -0500 |
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committer | Brandon Potter <brandon.potter@amd.com> | 2016-12-02 18:01:55 -0500 |
commit | 86b375f2f3c5d039a74be6481f11426fb51a5e38 (patch) | |
tree | 180165468bab4c28fd4d76712e7a31d19f9613e7 /src/arch/hsail | |
parent | 3bb3db6194bae29f03dfa40f589ff024232ee96c (diff) | |
download | gem5-86b375f2f3c5d039a74be6481f11426fb51a5e38.tar.xz |
hsail: add popcount type and generate popcount instructions
Diffstat (limited to 'src/arch/hsail')
-rw-r--r-- | src/arch/hsail/Brig_new.hpp | 2 | ||||
-rwxr-xr-x | src/arch/hsail/gen.py | 7 | ||||
-rw-r--r-- | src/arch/hsail/insts/decl.hh | 20 |
3 files changed, 27 insertions, 2 deletions
diff --git a/src/arch/hsail/Brig_new.hpp b/src/arch/hsail/Brig_new.hpp index 60e6f4dea..95fcf4d46 100644 --- a/src/arch/hsail/Brig_new.hpp +++ b/src/arch/hsail/Brig_new.hpp @@ -1455,6 +1455,8 @@ struct BrigInstSourceType { uint16_t reserved; //.defValue=0 }; +typedef BrigInstSourceType BrigInstPopcount; + struct BrigOperandAddress { BrigBase base; BrigCodeOffset32_t symbol; //.wtype=ItemRef<DirectiveVariable> diff --git a/src/arch/hsail/gen.py b/src/arch/hsail/gen.py index 0cc111e53..d07d49c28 100755 --- a/src/arch/hsail/gen.py +++ b/src/arch/hsail/gen.py @@ -211,6 +211,7 @@ header_templates = { 'ExtractInsertInst': header_template_1dt, 'CmpInst': header_template_2dt, 'CvtInst': header_template_2dt, + 'PopcountInst': header_template_2dt, 'LdInst': '', 'StInst': '', 'SpecialInstNoSrc': header_template_nodt, @@ -426,6 +427,7 @@ exec_templates = { 'ClassInst': exec_template_1dt_2src_1dest, 'CmpInst': exec_template_2dt, 'CvtInst': exec_template_2dt, + 'PopcountInst': exec_template_2dt, 'LdInst': '', 'StInst': '', 'SpecialInstNoSrc': exec_template_nodt_nosrc, @@ -555,7 +557,7 @@ def gen(brig_opcode, types=None, expr=None, base_class='ArithInst', dest_is_src_flag = str(dest_is_src).lower() # for C++ if base_class in ['ShiftInst']: expr = re.sub(r'\bsrc(\d)\b', r'src_val\1', expr) - elif base_class in ['ArithInst', 'CmpInst', 'CvtInst']: + elif base_class in ['ArithInst', 'CmpInst', 'CvtInst', 'PopcountInst']: expr = re.sub(r'\bsrc(\d)\b', r'src_val[\1]', expr) else: expr = re.sub(r'\bsrc(\d)\b', r'src_val\1', expr) @@ -674,7 +676,8 @@ gen('Xor', bit_types, 'src0 ^ src1') gen('Bitselect', bit_types, '(src1 & src0) | (src2 & ~src0)') gen('Firstbit',bit_types, 'firstbit(src0)') -gen('Popcount', ('B32', 'B64'), '__builtin_popcount(src0)') +gen('Popcount', ('U32',), '__builtin_popcount(src0)', 'PopcountInst', \ + ('sourceType', ('B32', 'B64'))) gen('Shl', arith_int_types, 'src0 << (unsigned)src1', 'ShiftInst') gen('Shr', arith_int_types, 'src0 >> (unsigned)src1', 'ShiftInst') diff --git a/src/arch/hsail/insts/decl.hh b/src/arch/hsail/insts/decl.hh index 4c0bc9ce1..919a4d9d4 100644 --- a/src/arch/hsail/insts/decl.hh +++ b/src/arch/hsail/insts/decl.hh @@ -725,6 +725,26 @@ namespace HsailISA } }; + template<typename DestDataType, typename SrcDataType> + class PopcountInst : + public CommonInstBase<typename DestDataType::OperandType, + typename SrcDataType::OperandType, 1> + { + public: + std::string opcode_suffix() + { + return csprintf("_%s_%s", DestDataType::label, SrcDataType::label); + } + + PopcountInst(const Brig::BrigInstBase *ib, const BrigObject *obj, + const char *_opcode) + : CommonInstBase<typename DestDataType::OperandType, + typename SrcDataType::OperandType, + 1>(ib, obj, _opcode) + { + } + }; + class SpecialInstNoSrcNoDest : public HsailGPUStaticInst { public: |