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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-03 13:10:26 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
| commit | 2113b21996d086dab32b9fd388efe3df241bfbd2 (patch) | |
| tree | 26d944027f726dde3ec49b67538663ccc41bcad3 /src/arch/hsail | |
| parent | 59505f7305cc3f3b7637233fd2d231bd7f561e80 (diff) | |
| download | gem5-2113b21996d086dab32b9fd388efe3df241bfbd2.tar.xz | |
misc: Substitute pointer to Request with aliased RequestPtr
Every usage of Request* in the code has been replaced with the
RequestPtr alias. This is a preparing patch for when RequestPtr will be
the typdefed to a smart pointer to Request rather then a raw pointer to
Request.
Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10995
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Diffstat (limited to 'src/arch/hsail')
| -rw-r--r-- | src/arch/hsail/insts/mem.hh | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/src/arch/hsail/insts/mem.hh b/src/arch/hsail/insts/mem.hh index 36a6cbc79..68a61feea 100644 --- a/src/arch/hsail/insts/mem.hh +++ b/src/arch/hsail/insts/mem.hh @@ -461,9 +461,10 @@ namespace HsailISA *d = gpuDynInst->wavefront()->ldsChunk-> read<c0>(vaddr); } else { - Request *req = new Request(0, vaddr, sizeof(c0), 0, - gpuDynInst->computeUnit()->masterId(), - 0, gpuDynInst->wfDynId); + RequestPtr req = new Request(0, + vaddr, sizeof(c0), 0, + gpuDynInst->computeUnit()->masterId(), + 0, gpuDynInst->wfDynId); gpuDynInst->setRequestFlags(req); PacketPtr pkt = new Packet(req, MemCmd::ReadReq); @@ -588,7 +589,7 @@ namespace HsailISA gpuDynInst->statusBitVector = VectorMask(1); gpuDynInst->useContinuation = false; // create request - Request *req = new Request(0, 0, 0, 0, + RequestPtr req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), 0, gpuDynInst->wfDynId); req->setFlags(Request::ACQUIRE); @@ -1014,7 +1015,7 @@ namespace HsailISA gpuDynInst->execContinuation = &GPUStaticInst::execSt; gpuDynInst->useContinuation = true; // create request - Request *req = new Request(0, 0, 0, 0, + RequestPtr req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), 0, gpuDynInst->wfDynId); req->setFlags(Request::RELEASE); @@ -1065,7 +1066,7 @@ namespace HsailISA gpuDynInst->wavefront()->ldsChunk->write<c0>(vaddr, *d); } else { - Request *req = + RequestPtr req = new Request(0, vaddr, sizeof(c0), 0, gpuDynInst->computeUnit()->masterId(), 0, gpuDynInst->wfDynId); @@ -1488,7 +1489,7 @@ namespace HsailISA gpuDynInst->useContinuation = true; // create request - Request *req = new Request(0, 0, 0, 0, + RequestPtr req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), 0, gpuDynInst->wfDynId); req->setFlags(Request::RELEASE); @@ -1620,7 +1621,7 @@ namespace HsailISA "type.\n"); } } else { - Request *req = + RequestPtr req = new Request(0, vaddr, sizeof(c0), 0, gpuDynInst->computeUnit()->masterId(), 0, gpuDynInst->wfDynId, @@ -1675,7 +1676,7 @@ namespace HsailISA // the acquire completes gpuDynInst->useContinuation = false; // create request - Request *req = new Request(0, 0, 0, 0, + RequestPtr req = new Request(0, 0, 0, 0, gpuDynInst->computeUnit()->masterId(), 0, gpuDynInst->wfDynId); req->setFlags(Request::ACQUIRE); |