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| author | Alexandru Dutu <alexandru.dutu@amd.com> | 2016-09-16 12:36:20 -0400 |
|---|---|---|
| committer | Alexandru Dutu <alexandru.dutu@amd.com> | 2016-09-16 12:36:20 -0400 |
| commit | 68127ca3da543db0c2f3d131d2b3f3525a35ec50 (patch) | |
| tree | 1c8b1495755ef1344f72b25fa8d4b39626b99626 /src/arch/hsail | |
| parent | bd65ec07441cbb19fc2d3570da32a0205dad52c2 (diff) | |
| download | gem5-68127ca3da543db0c2f3d131d2b3f3525a35ec50.tar.xz | |
hsail: Fix disassembly of load instruction with 3 destination operands
Diffstat (limited to 'src/arch/hsail')
| -rw-r--r-- | src/arch/hsail/insts/mem_impl.hh | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/hsail/insts/mem_impl.hh b/src/arch/hsail/insts/mem_impl.hh index 3042e2201..e3529f914 100644 --- a/src/arch/hsail/insts/mem_impl.hh +++ b/src/arch/hsail/insts/mem_impl.hh @@ -93,6 +93,15 @@ namespace HsailISA this->dest_vect[1].disassemble(), this->addr.disassemble()); break; + case 3: + this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode, + segmentNames[this->segment], + MemDataType::label, + this->dest_vect[0].disassemble(), + this->dest_vect[1].disassemble(), + this->dest_vect[2].disassemble(), + this->addr.disassemble()); + break; case 4: this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s", this->opcode, |