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authorTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:43 -0400
committerTony Gutierrez <anthony.gutierrez@amd.com>2016-10-26 22:47:43 -0400
commit844fb845a51b15f13c7c744e0d5fdf5567c3da98 (patch)
tree407cd19c909cdf3cd4da7947ad86dfbd4470ef68 /src/arch/hsail
parentd327cdba078e0956596513b518731e9ec730723f (diff)
downloadgem5-844fb845a51b15f13c7c744e0d5fdf5567c3da98.tar.xz
gpu-compute, hsail: make the PC a byte address, not an instruction index
currently the PC is incremented on an instruction granularity, and not as an instruction's byte address. machine ISA instructions assume the PC is a byte address, and is incremented accordingly. here we make the GPU model, and the HSAIL instructions treat the PC as a byte address as well.
Diffstat (limited to 'src/arch/hsail')
-rw-r--r--src/arch/hsail/gpu_isa.hh3
-rw-r--r--src/arch/hsail/gpu_types.hh2
-rw-r--r--src/arch/hsail/insts/branch.hh4
-rw-r--r--src/arch/hsail/insts/gpu_static_inst.hh3
4 files changed, 7 insertions, 5 deletions
diff --git a/src/arch/hsail/gpu_isa.hh b/src/arch/hsail/gpu_isa.hh
index dbd816d91..caee776f1 100644
--- a/src/arch/hsail/gpu_isa.hh
+++ b/src/arch/hsail/gpu_isa.hh
@@ -38,6 +38,7 @@
#include <cstdint>
+#include "arch/hsail/gpu_types.hh"
#include "base/misc.hh"
#include "gpu-compute/misc.hh"
@@ -71,7 +72,7 @@ namespace HsailISA
uint32_t
advancePC(uint32_t old_pc, GPUDynInstPtr gpuDynInst)
{
- return old_pc + 1;
+ return old_pc + sizeof(RawMachInst);
}
private:
diff --git a/src/arch/hsail/gpu_types.hh b/src/arch/hsail/gpu_types.hh
index 4b3a66a9a..7b6689d67 100644
--- a/src/arch/hsail/gpu_types.hh
+++ b/src/arch/hsail/gpu_types.hh
@@ -51,7 +51,7 @@ namespace HsailISA
// our model uses to represent an actual instruction. In
// the case of HSAIL this is just an index into a list of
// instruction objects.
- typedef uint64_t RawMachInst;
+ typedef uint32_t RawMachInst;
// The MachInst is a representation of an instruction
// that has more information than just the machine code.
diff --git a/src/arch/hsail/insts/branch.hh b/src/arch/hsail/insts/branch.hh
index 3a520b216..6df6f766a 100644
--- a/src/arch/hsail/insts/branch.hh
+++ b/src/arch/hsail/insts/branch.hh
@@ -257,7 +257,7 @@ namespace HsailISA
{
Wavefront *w = gpuDynInst->wavefront();
- const uint32_t curr_pc = w->pc();
+ const uint32_t curr_pc M5_VAR_USED = w->pc();
const uint32_t curr_rpc = w->rpc();
const VectorMask curr_mask = w->execMask();
@@ -281,7 +281,7 @@ namespace HsailISA
}
// not taken branch
- const uint32_t false_pc = curr_pc + 1;
+ const uint32_t false_pc = nextInstAddr();
assert(true_pc != false_pc);
if (false_pc != rpc && true_mask.count() < curr_mask.count()) {
VectorMask false_mask = curr_mask & ~true_mask;
diff --git a/src/arch/hsail/insts/gpu_static_inst.hh b/src/arch/hsail/insts/gpu_static_inst.hh
index 5dcfe78d5..bb40411ed 100644
--- a/src/arch/hsail/insts/gpu_static_inst.hh
+++ b/src/arch/hsail/insts/gpu_static_inst.hh
@@ -42,6 +42,7 @@
* Defines the base class representing HSAIL GPU static instructions.
*/
+#include "arch/hsail/gpu_types.hh"
#include "gpu-compute/gpu_static_inst.hh"
class BrigObject;
@@ -54,7 +55,7 @@ namespace HsailISA
public:
HsailGPUStaticInst(const BrigObject *obj, const std::string &opcode);
void generateDisassembly();
- uint32_t instSize() { return 4; }
+ int instSize() const override { return sizeof(RawMachInst); }
bool isValid() const override { return true; }
protected: