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authorGabe Black <gblack@eecs.umich.edu>2007-08-07 15:19:26 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-08-07 15:19:26 -0700
commitfb6cdf09cb4cfe9f39fdc7381168883fae6816ec (patch)
tree749d30835f7f27edbd21f913e057c9bc922eb528 /src/arch/isa_parser.py
parentcae8d20633c0f43fdae23576adfb894284a7ee86 (diff)
downloadgem5-fb6cdf09cb4cfe9f39fdc7381168883fae6816ec.tar.xz
X86: Make a microcode branch microop.
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
Diffstat (limited to 'src/arch/isa_parser.py')
-rwxr-xr-xsrc/arch/isa_parser.py19
1 files changed, 19 insertions, 0 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 64a120c4c..fb398d152 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1464,6 +1464,25 @@ class MemOperand(Operand):
def makeAccSize(self):
return self.size
+class UPCOperand(Operand):
+ def makeConstructor(self):
+ return ''
+
+ def makeRead(self):
+ return '%s = xc->readMicroPC();\n' % self.base_name
+
+ def makeWrite(self):
+ return 'xc->setMicroPC(%s);\n' % self.base_name
+
+class NUPCOperand(Operand):
+ def makeConstructor(self):
+ return ''
+
+ def makeRead(self):
+ return '%s = xc->readNextMicroPC();\n' % self.base_name
+
+ def makeWrite(self):
+ return 'xc->setNextMicroPC(%s);\n' % self.base_name
class NPCOperand(Operand):
def makeConstructor(self):