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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-17 10:53:10 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-17 10:53:10 -0500 |
| commit | 220e99a29bb2531a8bba5e20125f5f182518fa6d (patch) | |
| tree | bcc65e82a88c69c57d8c2602983ca5fc774539f3 /src/arch/isa_parser.py | |
| parent | 9d0ca61b7e357ca5e83f97f8cb8f4f1037cc3eb5 (diff) | |
| download | gem5-220e99a29bb2531a8bba5e20125f5f182518fa6d.tar.xz | |
Compilation fix after messy merge.
--HG--
extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
Diffstat (limited to 'src/arch/isa_parser.py')
| -rwxr-xr-x | src/arch/isa_parser.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 5f6a33565..83cdf73bc 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1362,7 +1362,7 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscRegOperandWithEffect(%s)' % self.reg_spec + base = 'xc->readMiscRegOperandWithEffect(this, %s)' % self.src_reg_idx if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: |