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| author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:24:00 -0500 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
| commit | 00da08902918da13fccc3f2266b7b2f5d0080708 (patch) | |
| tree | b495a0ceba7e073adca005cf84a7575d0aad5f27 /src/arch/isa_parser.py | |
| parent | 0747a432d25ade2c197ca6393270e12606419872 (diff) | |
| download | gem5-00da08902918da13fccc3f2266b7b2f5d0080708.tar.xz | |
cpu: Added interface for vector reg file
This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different
models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
Diffstat (limited to 'src/arch/isa_parser.py')
| -rwxr-xr-x | src/arch/isa_parser.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 610197e38..759b50c0d 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1,4 +1,4 @@ -# Copyright (c) 2014 ARM Limited +# Copyright (c) 2014, 2016 ARM Limited # All rights reserved # # The license below extends only to copyright in the software and shall @@ -865,8 +865,8 @@ class OperandList(object): op_desc = self.find_base(op_base) if op_desc: if op_desc.ext != op_ext: - error('Inconsistent extensions for operand %s' % \ - op_base) + error ('Inconsistent extensions for operand %s' % \ + op_base) op_desc.is_src = op_desc.is_src or is_src op_desc.is_dest = op_desc.is_dest or is_dest else: |