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authorKevin Lim <ktlim@umich.edu>2006-10-31 14:44:23 -0500
committerKevin Lim <ktlim@umich.edu>2006-10-31 14:44:23 -0500
commit2fa535f7407ad2a7e1e2ec807b72d11a81fa25aa (patch)
tree29a33ada141edad37b9304227f411a0195520869 /src/arch/isa_parser.py
parente912080d12666482a942eae354e783c3d666c6c9 (diff)
parent7f39644609e19ada9e94c9bbb09c3e625fa6e8ed (diff)
downloadgem5-2fa535f7407ad2a7e1e2ec807b72d11a81fa25aa.tar.xz
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem --HG-- extra : convert_revision : 88fa7ae5cc32be068787ee381fae9d8de0e9bd0f
Diffstat (limited to 'src/arch/isa_parser.py')
-rwxr-xr-xsrc/arch/isa_parser.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index b235398f1..6504c7b32 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1316,7 +1316,7 @@ class ControlRegOperand(Operand):
def makeWrite(self):
if (self.ctype == 'float' or self.ctype == 'double'):
error(0, 'Attempt to write control register as FP')
- wb = 'xc->setMiscReg(%s, %s);\n' % (self.reg_spec, self.base_name)
+ wb = 'xc->setMiscRegWithEffect(%s, %s);\n' % (self.reg_spec, self.base_name)
wb += 'if (traceData) { traceData->setData(%s); }' % \
self.base_name
return wb