diff options
author | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
---|---|---|
committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2013-10-15 14:22:43 -0400 |
commit | 219c423f1fb0f9a559bfa87f9812426d5e2c3e29 (patch) | |
tree | 7980ae867c4642e710af7cd5d0ad7fe51c0b6687 /src/arch/isa_parser.py | |
parent | a830e63de71e5929b8ff8e334bc872faa9193a8b (diff) | |
download | gem5-219c423f1fb0f9a559bfa87f9812426d5e2c3e29.tar.xz |
cpu: rename *_DepTag constants to *_Reg_Base
Make these names more meaningful.
Specifically, made these substitutions:
s/FP_Base_DepTag/FP_Reg_Base/g;
s/Ctrl_Base_DepTag/Misc_Reg_Base/g;
s/Max_DepTag/Max_Reg_Index/g;
Diffstat (limited to 'src/arch/isa_parser.py')
-rwxr-xr-x | src/arch/isa_parser.py | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index ec0efe5e6..e4f81c173 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -610,12 +610,12 @@ class FloatRegOperand(Operand): c_dest = '' if self.is_src: - c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;' % \ + c_src = '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Reg_Base;' % \ (self.reg_spec) if self.is_dest: c_dest = \ - '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Base_DepTag;' % \ + '\n\t_destRegIdx[_numDestRegs++] = %s + FP_Reg_Base;' % \ (self.reg_spec) c_dest += '\n\t_numFPDestRegs++;' @@ -673,12 +673,12 @@ class ControlRegOperand(Operand): if self.is_src: c_src = \ - '\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;' % \ + '\n\t_srcRegIdx[_numSrcRegs++] = %s + Misc_Reg_Base;' % \ (self.reg_spec) if self.is_dest: c_dest = \ - '\n\t_destRegIdx[_numDestRegs++] = %s + Ctrl_Base_DepTag;' % \ + '\n\t_destRegIdx[_numDestRegs++] = %s + Misc_Reg_Base;' % \ (self.reg_spec) return c_src + c_dest |